Event Details

Asia and Europe

Time: 10-11am (GMT) 11am-12pm (CET) 3.30-4.30pm (IST)

Americas

Time: 10-11am (PST) 11am-12pm (MST) 12-1pm (CST) 1-2pm (EST)

 

Webinar Overview:

cocotb is a Python-based framework, created to enable the rapid construction of verification environments for digital designs. With many engineers having a working knowledge of Python, cocotb can prove a highly effective verification tool.

This webinar will help you get started by covering:

• The principles of cocotb co-simulation and how cocotb fits into the design and verification flow
• Communication between the Python world and VHDL/SystemVerilog designs
• Handling concurrency in cocotb
• Sychronization and timing for verifying RTL designs
• Structuring a cocotb test bench
• Running cocotb tests
• An example cocotb-driven simulation

This webinar is run in partnership with Aldec and will feature examples running in Riviera-PRO™ using the free online simulation environment from Doulos EDA Playground. Both VHDL and SystemVerilog designs under test will be shown.