Event Details View All Recorded Events Date Event Type Location Action Feb 12, 2026 VHDL-2019: Just the New Stuff - Part 5: Type System and Language Enhancements (EU) Time: 4:00 PM - 5:00 PM (CET) Abstract In this fifth webinar of the VHDL-2019: Just the New Stuff webinar series, we focus on some of the final pieces of VHDL-2019 capability. In particular, this presentation delves into the following updates and why they are important: 64-bit Integers Unspecified types as generic types Unspecified types on parameter interfaces Sequential declaration regions Closely related record types Signature for generic in formal designator You can find the recordings of the four previous sessions of the webinar series. VHDL-2019: Just the New Stuff Part 1: Interfaces, Conditional Analysis, File IO, and The New EnvironmentPart 2: Protected Types and Verification Data StructuresPart 3: RTL EnhancementsPart 4: Testbench Enhancements About VHDL-2019 VHDL-2019 was requested by users, ranked by users, scrutinized by users, written by users, and balloted by the VHDL community. As such, it should be clear to the vendor (simulation and synthesis) community that the users want these features. Through its revisions, 1987, 1993, 2002, 2008, and now 2019, VHDL has evolved to be a capable design and verification language. Aldec started their implementation of VHDL-2019 prior to the standard being completed and is well into their implementation. If your vendor cannot tell you definitively if and when they will support the new features you want to use on your VHDL projects, then maybe it is time to find a vendor who will. What about Verilog and SystemVerilog? Despite overwhelming marketing for SystemVerilog, it is clear from the Wilson Verification Survey that VHDL is the preferred FPGA design and verification language. For many applications, FPGA is the future. Just like in the software world, FLASH is usually preferred over ROM. The VHDL standards committee’s work is never done. It takes a collaboration of people with different skills to successfully update the standard. Some of these members are language experts, some design experts, and some verification experts. Join us in writing the next revision. See: http://www.eda-twiki.org/cgi-bin/view.cgi/P1076/WebHome. Agenda: 50 min presentation/live demo 10 min Q&A Presenter BIO Jim Lewis, VHDL User, Designer, Verification Engineer, Trainer, OSVVM developer, and IEEE VHDL ChairThe presenter, Jim Lewis, is an innovator and leader in the VHDL community. He has 30 plus years of design and teaching experience. He is the Chair of the IEEE 1076 VHDL Standards Working Group. He is a co-founder of the Open Source VHDL Verification Methodology (OSVVM) and the chief architect of the packages and methodology. He is an expert VHDL trainer for SynthWorks Design Inc. In his design practice, he has created designs for print servers, IMA E1/T1 networking, fighter jets, video phones, and space craft. Whether teaching, developing OSVVM, doing consulting work, or working on the IEEE VHDL standard, Mr Lewis brings a deep understanding of VHDL to architect solutions that solve difficult problems in simple ways. Webinar Online Register
