Event Details

Time: 11:00 AM - 12:00 PM (PDT)

 

Abstract

As FPGA technology continues to evolve - to provide us with full-blown SoCs with CPU, GPU, and high-speed peripherals, for example, joining the traditional programmable logic area - design verification becomes increasingly challenging. Lab-based FPGA testing and bring-up alone are clearly insufficient, especially for safety-critical designs, and FPGA teams are adopting advanced design verification methodologies and techniques to develop homegrown verification processes.

 

In this three-part webinar series, we will discuss design verification with a focus on creating an advanced simulation-based verification process; from verification planning and team organization, and moving on to regression setup, functional coverage collection, randomization and ‘verification done’ definitions. We will also show you how to develop simple yet powerful and reusable testbenches using Verilog and SystemVerilog constructs and how to functionally verify designs in the most efficient way.

 

In part 2 of this webinar series, we will show you important verification patterns providing solutions to repeatable randomization, error management and end-of-test checks. We will also provide an overview of how to define, develop and re-use verification components such as drivers, responders, and monitors. Then, we will talk about how to develop testbenches, and how to validate their correctness with reporting and statistics collection. We will provide code examples to illustrate the topics of discussion.

 

Agenda:

• Common Verification Patterns:
  o Repeatable Randomization
  o Reporting, Error management
  o End-of-Test Procedure
• Verification Components (VC) Development:
  o Verification Component Types
  o Defining Transactions for VC Development
  o Legal and Error Operation Modes
  o Controllable Randomization
  o Verification in Standalone Testbenches
• Testbench Development and Verification:
  o Statistical methods for Testbench Validation
  o Scripting Support
• Demo with example design and testbench
• Conclusion
• Q&A

Webinar Duration:

• 45 min presentation/live demo
• 15 min Q&A

 

Presenter BIO

Alexander Gnusin, Design Verification Technologist, Aldec

Alexander Gnusin accumulated 27 years of hands-on experience in various aspects of ASIC and FPGA design and verification. As a verification prime for a multi-million gates project in companies such as IBM, Nortel, Ericsson and Synopsys Inc, he combined various verification methods such as static linting, formal property checking, dynamic simulation and hardware-assisted acceleration to efficiently achieve design verification goals. He received his M.S. in Electronics from Technion, Israel Institute of Technology.