Event Details

View All Recorded Events
Date Event Type Location Action
Dec 03, 2020 Debugging Multi-Core Designs using Vitis + Aldec Riviera-PRO Co-Simulation for Zynq US+ MPSoC (EU)

Time: 3:00 PM – 4:00 PM (CEST)



The highly integrated Xilinx® Zynq™ UltraScale+ MPSoC architecture provides the ARM CoreSight architecture for the hardware debugging methodology. But the development process does not necessarily require hardware, and the validation process can be accelerated with unit tests or partial system tests. It needs different approaches of validation tools which can be used independently, but as important is also the co-simulation for the heterogeneous MPSoC architecture when the programmable hardware requires processor communication to the programmable logic resources such as shared memories, control logic, HDL user peripherals, DMA and interrupt handling. This webinar will give you a better understanding of using the Xilinx Vitis tool and a higher value when using Riviera-PRO simulator supporting the co-simulation.



First, we will have a quick look into the Zynq UltraScale+ MPSoC architecture to better understand the necessity for simulation and emulation needs. The Xilinx Vitis tool provides a unified platform environment for multi-processing and you will see the debugging methodology for multi-core debugging. The processor system is immediately supported with the Vitis integrated QEMU but with the addition of programmable logic modules it requires the System-C based HDL models and the AXI adapters between the worlds of processing system and programmable logic. And exactly this is provided as an integrated solution when using Riviera-PRO simulator. Attendees will learn how they can improve their debugging productivity for these MPSoC architectures.




  •  Zynq UltraScale+ MPSoC Review
  •  Vitis Multicore Debugging
  •  Xilinx QEMU Co-Simulation
  •  Device Tree Requirements
  •  Co-Simulation with Riviera-PRO
  •  Demo - MultiCore Debug Session using Vitis and Riviera-PRO
  •  Q&A


Presenter Bio:

After completing his university studies, Ernst Wehlage started in Darmstadt, Germany in the digital development of professional video systems for the future HDTV technology. FPGA technologies were used in complex systems at an early stage in order to achieve high data rates, which were decisive for the development of new, innovative film and video systems in high-resolution real-time processing. With over 30 years of professional experience in training and the application of programmable logic, the fascination of these possibilities is unbroken, as continually innovative technological leaps give hardware and software developers ever better methods. He has been a trainer in the PLC2 team since 2001 for almost all subject areas of the PLC2 training courses, projects FPGA and MPSoC based systems on behalf of customers and advises developers on how to solve their development tasks.


Webinar Online Register
Ask Us a Question
Ask Us a Question
Captcha ImageReload Captcha
Incorrect data entered.
Thank you! Your question has been submitted. Please allow 1-3 business days for someone to respond to your question.
Internal error occurred. Your question was not submitted. Please contact us using Feedback form.
We use cookies to ensure we give you the best user experience and to provide you with content we believe will be of relevance to you. If you continue to use our site, you consent to our use of cookies. A detailed overview on the use of cookies and other website information is located in our Privacy Policy.