Aldec - Products - FPGA Simulation

FPGA Design Creation and Simulation

Active-HDL™ is a Windows® based integrated FPGA Design Creation and Simulation solution. Active-HDL includes a full HDL graphical design tool suite and RTL/gate-level mixed-language simulator. The design flow manager evokes 90 plus EDA and FPGA tools, during design entry, simulation, synthesis and implementation flows, making it a seamless and flexible design creation and simulation platform. Active-HDL supports industry leading FPGA devices, from Altera®, Atmel®, Lattice®, Microsemi™ (Actel), Quicklogic®, Xilinx® and more.

Top Features

Multi-FPGA & EDA Tool Design Flow Manager
Graphical Design entry & editing
Code2Graphics and Graphics2Code
Pre-compiled FPGA vendor libraries
IEEE Language Support: VHDL, Verilog®, SystemVerilog
Design, SystemC
Advanced Debugging & Code Coverage
IP Encryption and Xilinx® Secure IP support
ABV, Assertion-Based Verification (SVA, PSL, OVA)
DSP Co-simulation with MATLAB®/Simulink®
HTML and PDF Design Documentation
Integration with Riviera-PRO and ALINT
HDL code analysis and navigation tool
IP Encryption, Altera® IP and Xilinx® Secure IP support

Block Diagram Editor

HDL Editor

State Diagram Editor

Waveform Viewer