The speed of the HDL simulator is the primary bottleneck of the design cycle when it comes to verification. Limiting the number of simulation tests because there is not enough time is alarming, and raises doubt about the completeness of verification. With Aldec's HES/DVM XCELL, simulation can now be accelerated in excess of 10x in comparison to pure HDL simulation.
Simulation is accelerated by placing resource-hungry modules in the FPGA board while the simulation is controlled by the HDL simulator. This verification method combines benefits of HDL simulation (signal visibility) and prototyping (speed). Although the HDL designs are simulated in the FPGA board, designers can still use the HDL simulator as the main debugging tool because all design output signals are fed back to the simulator’s waveform viewer. This allows debugging of the design at silicon-level accuracy and faster simulation runs even at the early stage of the design cycle, leading to more discovered bugs and errors in a relatively much shorter time frame.
- Speed — Acceleration in excess of 10x in comparison with pure HDL simulation. This allows more tests to be run which increases the coverage of the testbench or increases the number of different testbenches that can be executed.
- Accelerated Debugging— Accelerated simulation is incomplete without accelerated debugging. HES/DVM XCELL is equipped with debugging tools such as Black Box and Mirror Box which allow quick fixes of the HDL code without rebuilding the FPGA, avoiding the long wait time during synthesis and implementation.
- Silicon-Level Accuracy — The engineer can start functional verification of design immediately in the FPGA board ensuring silicon-level accuracy, minimizing the errors and bugs that can come up during prototyping. Additionally, static probes are available to monitor ports/signals even at the lowest level of design hierarchy that can be viewed in the simulator’s waveform viewer, providing full visibility of the design.