...
...

Multimedia

-OR-

Results

Name Products Type Action
76 results (page 1/4)
100% Signal Visibility during Emulation Dynamic Debug with HVD Technology   
Abstract: When it comes to debugging during emulation, engineers are forced to use multiple applications to ensure proper hardware signal data extraction and visualization. Learn from this webinar a leading edge technology that intelligently extracts data from the FPGA emulator to provide 100% signal visibility during emulation. This approach delivers up to 70% bandwidth savings in the critical emulator communication channel. Both dynamic and static probes from emulation can also be visualized in the Riviera-PRO waveform viewer preserving the original signal names and hierarchy paths and providing complete traceability to the design’s RTL source code. Play webinar   
HES-DVM Recorded Webinars
Accelerate DSP Design Development: Tailored Flows   
Learn how to achieve better Digital Signal Processing (DSP) design productivity using Aldec’s integrated design flows, enabled by a number of unique technologies, features, and industry partnerships available within Aldec Riviera-PRO™ design and verification platform. You will learn about the essential and innovative features in the RTL simulation environment that are important to signal processing: Model-based design flow integration, Floating-point aware RTL debugging tools, Dedicated protocol analysis tools, Full support for FPGA silicon vendors. Play webinar   
Active-HDL, Riviera-PRO Recorded Webinars
Accelerate SoC Simulation Time of Newer Generation FPGAs   
Functional verification of a design at the three design stages (RTL, Gate-Level and Post-Route) are essential steps to ensure correct behavior of a design according to requirements, however they are limited by HDL simulator speed. While HDL simulators offer advanced debugging capabilities and provide robust design coverage information, their speed is the primary bottleneck of the design cycle when it comes to verification. This webinar will discuss a faster, safer, and more thorough verification environment that combines the robustness of an HDL simulator with the speed of FPGA prototyping boards. Play webinar   
HES-DVM, HES-7 Recorded Webinars
Advanced Dataflow    Active-HDL Demonstration Videos
Aldec and SynthWorks: OS-VVM: Open Source - VHDL Verification Methodology   
Open Source - VHDL Verification Methodology (OS-VVM™) provides advanced verification capabilities to VHDL teams. Attendees will learn how to add functional coverage, constrained random test, and coverage driven random test to their current testbenches. OS-VVM has a straight-forward usage model that allows the addition of functional coverage, constrained random, and coverage driven random features to a testbench in part or in whole. This webinar demonstrates how the addition of Functional Coverage to testbenches is necessary - even with directed tests. Constrained Random or Coverage Driven randomization can be added when and where needed, and there is even the ability to mix directed, algorithmic, file-based, constrained random, and coverage driven random methods. OS-VVM is open source package based. It compiles under VHDL-2008 or VHDL-2002 (with minor adaptations, and has been produced as a joint effort between Aldec and SynthWorks, both companies committed to provide continued support to VHDL design community. Play webinar   
Active-HDL, Riviera-PRO Recorded Webinars
ARM Cortex SoC Prototyping Platform for Industrial Applications   
Modern industrial systems are faced with many key design challenges including: system complexity, real-time performance requirements, evolving standards, and rising costs. ASIC prototyping platforms allow designers to implement and verify functionality of industrial systems at-speed prior to silicon tape-out, saving money from costly re-spins. In this webinar, we demonstrate how to tackle industrial design applications with Aldec’s HES-7™, which supports ARM® Cortex™-A9 based designs by leveraging Xilinx® Zynq® All Programmable SoC. Play webinar   
HES-7 Recorded Webinars
ASIC/SoC Prototyping with Aldec’s new HES-7 Board   
Aldec's newly released FPGA-based prototyping platform, HES-7™, leverages Xilinx® Virtex®-7 FPGA. Xilinx has introduced a new Stacked Silicon Interconnect technology (SSI), enabling a single Virtex-7 to have 2M logic cells, making it the industry’s largest capacity FPGA. This webinar will provide an overview of modifications to previous Xilinx architecture and the structuring of SSI technology. The webinar will also present how the Virtex-7 benefits FPGA-based prototyping platforms, and will also provide an overview of HES-7 key features. Play webinar   
HES-7 Recorded Webinars
Assertions - A Practical Introduction for HDL Designers   
The majority of FPGA designers who are proficient in traditional HDLs might have heard about assertions, but haven’t had time to try them out. Designers should be aware that assertions are quickly becoming standard part of both design and verification process, so learning how to use them is a future necessity. This webinar provides quick and easy introduction to the basic ideas and applications of assertions: sequences, properties, assert and cover commands, etc. Practical examples are used both during presentation and live demonstration in the simulator. Play webinar   
Active-HDL, Riviera-PRO Recorded Webinars
Best Design Practices for High-Capacity FPGA Devices   
With the latest FPGA technology advancements and release of high capacity devices such as Xilinx® Virtex®-7 and Altera® Stratix®-V, design teams face more challenges producing safe and clean HDL (RTL, FPGA) code. In this presentation, we will focus on the design techniques that will result in the code running most optimally on the large FPGA designs, and be free of timing and synchronization issues. Play webinar   
ALINT Recorded Webinars
Better Coverage in VHDL   
Abstract: Experienced users of VHDL simulation with testbenches appreciate additional layer of safety that Coverage Analysis gives them. But are all kinds of coverage equally beneficial? While Code Coverage is certainly useful, it really verifies quality of the testbench, not the design itself. In this webinar we will show how to improve quality of the design using Property Coverage and Functional Coverage (with help of OS-VVM). Play webinar   
Active-HDL, Riviera-PRO Recorded Webinars
Block Diagram Editor    Active-HDL Demonstration Videos
Bookmarks, Delta Cycle and Virtual Grouping in Waveform Viewer    Riviera-PRO Demonstration Videos
Bridging Analog and Digital Verification   
Co-Webinar with Tanner. Abstract: Creating and verifying a mixed-signal IC design (a chip containing both analog and digital parts) is a challenge. SPICE based simulation provides the accuracy needed by the analog design but is too slow to deal with digital part. Event-driven digital simulation can handle digital portion, but fails when dealing with the analog design. The best method of solving this verification problem is to create a smart interface between the SPICE engine and the high-performance digital simulator. Play webinar   
Active-HDL Recorded Webinars
Browsing, Finding and Measuring in Waveform Viewer    Riviera-PRO Demonstration Videos
Closed Loop Verification of Large Designs   
Abstract: Modern digital designs reached sizes so huge that traditional, simplistic verification no longer works. Large number of design sources, multiple teams and tools using them, almost infinite stream of results they produce - all those factors create new management challenges. Our webinar will show how verification planning, simulation and regression management can be easily handled using Agnisys and Aldec tools.  Play webinar   
Riviera-PRO Recorded Webinars
Code Coverage    Active-HDL Demonstration Videos
Comparing Datasets    Riviera-PRO Demonstration Videos
Compilation and Simulation    Active-HDL Demonstration Videos
CyberWorkBench: C-based High Level Synthesis and Verification   
CyberWorkbench is a C-based integrated environment developed by NEC over the period of twenty years. C-based design flow allows designers to achieve higher design efficiency, low area and high performance for ASIC and FPGA chips. This “All-in-C” product includes all the tools needed for efficient C-based design such as a behavioral synthesizer, simulator and formal verifier. Play webinar   
CyberWorkBench Recorded Webinars
Datasets, Hierarchy Viewer, Object Viewer    Riviera-PRO Demonstration Videos