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Recorded Webinars

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Results

Name Products Type Action
44 results (page 1/3)
100% Signal Visibility during Emulation Dynamic Debug with HVD Technology   
Abstract: When it comes to debugging during emulation, engineers are forced to use multiple applications to ensure proper hardware signal data extraction and visualization. Learn from this webinar a leading edge technology that intelligently extracts data from the FPGA emulator to provide 100% signal visibility during emulation. This approach delivers up to 70% bandwidth savings in the critical emulator communication channel. Both dynamic and static probes from emulation can also be visualized in the Riviera-PRO waveform viewer preserving the original signal names and hierarchy paths and providing complete traceability to the design’s RTL source code. Play webinar   
HES-DVM Recorded Webinars
Accelerate DSP Design Development: Tailored Flows   
Learn how to achieve better Digital Signal Processing (DSP) design productivity using Aldec’s integrated design flows, enabled by a number of unique technologies, features, and industry partnerships available within Aldec Riviera-PRO™ design and verification platform. You will learn about the essential and innovative features in the RTL simulation environment that are important to signal processing: Model-based design flow integration, Floating-point aware RTL debugging tools, Dedicated protocol analysis tools, Full support for FPGA silicon vendors. Play webinar   
Active-HDL, Riviera-PRO Recorded Webinars
Accelerate SoC Simulation Time of Newer Generation FPGAs   
Functional verification of a design at the three design stages (RTL, Gate-Level and Post-Route) are essential steps to ensure correct behavior of a design according to requirements, however they are limited by HDL simulator speed. While HDL simulators offer advanced debugging capabilities and provide robust design coverage information, their speed is the primary bottleneck of the design cycle when it comes to verification. This webinar will discuss a faster, safer, and more thorough verification environment that combines the robustness of an HDL simulator with the speed of FPGA prototyping boards. Play webinar   
HES-DVM, HES-7 Recorded Webinars
Aldec and SynthWorks: OS-VVM: Open Source - VHDL Verification Methodology   
Open Source - VHDL Verification Methodology (OS-VVM™) provides advanced verification capabilities to VHDL teams. Attendees will learn how to add functional coverage, constrained random test, and coverage driven random test to their current testbenches. OS-VVM has a straight-forward usage model that allows the addition of functional coverage, constrained random, and coverage driven random features to a testbench in part or in whole. This webinar demonstrates how the addition of Functional Coverage to testbenches is necessary - even with directed tests. Constrained Random or Coverage Driven randomization can be added when and where needed, and there is even the ability to mix directed, algorithmic, file-based, constrained random, and coverage driven random methods. OS-VVM is open source package based. It compiles under VHDL-2008 or VHDL-2002 (with minor adaptations, and has been produced as a joint effort between Aldec and SynthWorks, both companies committed to provide continued support to VHDL design community. Play webinar   
Active-HDL, Riviera-PRO Recorded Webinars
ARM Cortex SoC Prototyping Platform for Industrial Applications   
Modern industrial systems are faced with many key design challenges including: system complexity, real-time performance requirements, evolving standards, and rising costs. ASIC prototyping platforms allow designers to implement and verify functionality of industrial systems at-speed prior to silicon tape-out, saving money from costly re-spins. In this webinar, we demonstrate how to tackle industrial design applications with Aldec’s HES-7™, which supports ARM® Cortex™-A9 based designs by leveraging Xilinx® Zynq® All Programmable SoC. Play webinar   
HES-7 Recorded Webinars
ASIC/SoC Prototyping with Aldec’s new HES-7 Board   
Aldec's newly released FPGA-based prototyping platform, HES-7™, leverages Xilinx® Virtex®-7 FPGA. Xilinx has introduced a new Stacked Silicon Interconnect technology (SSI), enabling a single Virtex-7 to have 2M logic cells, making it the industry’s largest capacity FPGA. This webinar will provide an overview of modifications to previous Xilinx architecture and the structuring of SSI technology. The webinar will also present how the Virtex-7 benefits FPGA-based prototyping platforms, and will also provide an overview of HES-7 key features. Play webinar   
HES-7 Recorded Webinars
Assertions - A Practical Introduction for HDL Designers   
The majority of FPGA designers who are proficient in traditional HDLs might have heard about assertions, but haven’t had time to try them out. Designers should be aware that assertions are quickly becoming standard part of both design and verification process, so learning how to use them is a future necessity. This webinar provides quick and easy introduction to the basic ideas and applications of assertions: sequences, properties, assert and cover commands, etc. Practical examples are used both during presentation and live demonstration in the simulator. Play webinar   
Active-HDL, Riviera-PRO Recorded Webinars
Best Design Practices for High-Capacity FPGA Devices   
With the latest FPGA technology advancements and release of high capacity devices such as Xilinx® Virtex®-7 and Altera® Stratix®-V, design teams face more challenges producing safe and clean HDL (RTL, FPGA) code. In this presentation, we will focus on the design techniques that will result in the code running most optimally on the large FPGA designs, and be free of timing and synchronization issues. Play webinar   
ALINT Recorded Webinars
Better Coverage in VHDL   
Abstract: Experienced users of VHDL simulation with testbenches appreciate additional layer of safety that Coverage Analysis gives them. But are all kinds of coverage equally beneficial? While Code Coverage is certainly useful, it really verifies quality of the testbench, not the design itself. In this webinar we will show how to improve quality of the design using Property Coverage and Functional Coverage (with help of OS-VVM). Play webinar   
Active-HDL, Riviera-PRO Recorded Webinars
Bridging Analog and Digital Verification   
Co-Webinar with Tanner. Abstract: Creating and verifying a mixed-signal IC design (a chip containing both analog and digital parts) is a challenge. SPICE based simulation provides the accuracy needed by the analog design but is too slow to deal with digital part. Event-driven digital simulation can handle digital portion, but fails when dealing with the analog design. The best method of solving this verification problem is to create a smart interface between the SPICE engine and the high-performance digital simulator. Play webinar   
Active-HDL Recorded Webinars
Closed Loop Verification of Large Designs   
Abstract: Modern digital designs reached sizes so huge that traditional, simplistic verification no longer works. Large number of design sources, multiple teams and tools using them, almost infinite stream of results they produce - all those factors create new management challenges. Our webinar will show how verification planning, simulation and regression management can be easily handled using Agnisys and Aldec tools.  Play webinar   
Riviera-PRO Recorded Webinars
CyberWorkBench: C-based High Level Synthesis and Verification   
CyberWorkbench is a C-based integrated environment developed by NEC over the period of twenty years. C-based design flow allows designers to achieve higher design efficiency, low area and high performance for ASIC and FPGA chips. This “All-in-C” product includes all the tools needed for efficient C-based design such as a behavioral synthesizer, simulator and formal verifier. Play webinar   
CyberWorkBench Recorded Webinars
Decrypting Encryption in HDL Design and Verification   
Abstract: The issue of securing information flow was very important in the past (mainly in diplomacy and military applications) and became even more important recently, with new applications such as banking (ATM transactions), on-line commerce (e-store transactions), media (pay-per-view contents) and hardware design (secure IP delivery). All those applications face one common problem nicely described in the old joke: the only truly secure information is the one that cannot be read by anybody. Both hardware designers and tool designers must find the balance between security and usability, which can be achieved only by implementing well tested algorithms and workflow. Using Aldec implementation of Secure IP Delivery as the vehicle, this presentation provides informative overview of recommended ciphers and methodologies that can be used by a wide, technical audience.  Play webinar   
Active-HDL, Riviera-PRO Recorded Webinars
DO-254 - How to Increase Verification Coverage by Test (Aldec and Altera)   
As described in DO-254, any inability to verify specific requirements by test on the device itself must be justified, and alternative means must be provided. Certification authorities favor verification by test for formal verification credits because of the simple fact that hardware flies not simulation models. Requirements describing FPGA I/Os must be verified by test. The problem is that testing the FPGA device at the board level provides very low FPGA I/O controllability and visibility, therefore, giving you the inability to verify specific requirements by test. In this webinar, Aldec will demonstrate how you can verify all FPGA level requirements by test. All of the requirements verified during simulation can be repeated and verified in the target device. We will demonstrate a unique solution that enables requirements-based test by reusing the testbench as test vectors for testing the device at-speed. In this webinar, Altera will also share insights into the market trends observed from different applications and discuss some of the solution strategies that will address the system reliability concerns. Play webinar   
DO-254/CTS Recorded Webinars
DO-254 FPGA Level In-Target Testing   
Functional verification of digital designs in real hardware has been a serious undertaking when developing under DO-254 standard. Section 6.2 Verification Process of RTCA/DO-254 specifies that requirements must be preserved and verified from RTL simulation stage to hardware verification stage. Learn in this webinar examples of common challenges that are usually encountered during hardware verification, and more importantly, the solution to overcome these challenges. This webinar will highlight a unique methodology to replay RTL simulation in the target device at-speed that can significantly reduce the verification cycle. Play webinar   
DO-254/CTS Recorded Webinars
DO-254 Requirements Traceability   
Complex custom micro-coded devices such as PLDs, FPGAs and ASICs used in commercial airborne hardware are subject to the development process outlined in the DO-254 guidance. This means that the design and verification for these types of devices must follow the strict requirements-based process described in DO-254. The primary purpose of DO-254 is to provide assurance that the device under test meets its intended functions under all foreseeable operating conditions. Requirements express the functions of the device under test, and therefore it is crucial that requirements drive the design and verification activities. Requirements traceability helps to ensure that design and verification activities are requirements-based. In this webinar, we will describe requirements traceability according to DO-254 guidance in the context of FPGAs, and we will provide explanations as to what it means for the applicants to meet the objectives for traceability. We will also describe the underlying purpose of traceability and the resulting benefits that can be achieved when done correctly. Play webinar   
Spec-TRACER, DO-254/CTS Recorded Webinars
DO-254 Verification Strategies   
As a best-practice standard, efficient ASIC and FPGA project planners will allocate 1/3 of the project cycle to design and 2/3 of the project cycle to verification. The best of these planners will bias toward even more verification-hours and innovative verification strategies whenever possible, because the great reality of schedule-time allocated to verification is that THERE’S NEVER ENOUGH TIME. When an FPGA or ASIC is destined for an avionics product, effective design of that DO-254-qualified device is even more dependent-upon good verification strategies and practices. Good verification strategies will use those precious hours more effectively – and will also consistently prove to be more useful when combined with a comprehensive exploitation of well-written requirements and compliance with a well-constructed verification process, planned in advance of the work. In this webinar, we will discuss various verification strategies and how they can be applied to successful verification of a design in a DO-254 Levels A/B flow. Play webinar   
DO-254/CTS Recorded Webinars
Don't Be Afraid of UVM (UVM for Hardware Designers)   
Hardware Designers are usually very busy doing their work and have little time left for experimentation with new methodologies. Unfortunately for them, official documentation of UVM (Universal Verification Methodology) was written by Verification Engineers for Verification Engineers, concentrating on high-level features and completely neglecting lower-level details such as connecting UVM testbench to your design. Our webinar starts with solid review of SystemVerilog interfaces with special attention paid to Virtual Interfaces. Then it proceeds to Sequences and other Data Items, processed by Sequencers and fed to the design under test via Drivers. The role of Monitors and Scoreboards in analysis of results is explained. The presentation concludes with environment configuration and running test from the top-level module. Play webinar   
Riviera-PRO Recorded Webinars
Efficient Verification Approach for DO-254 designs   
Abstract: The main purpose of DO-254 Verification Process (Chapter 6.2 of DO-254 Specification) is not merely to verify the functionality of the design but more importantly to obtain assurance that the hardware implementation meets the requirements defined in the early stages of DO-254 targeted project. It is absolutely critical to ensure that the same requirements are preserved in all stages of design and verification from planning to hardware testing. Learn in this webinar an effective approach to verifying your design from the RTL to hardware preserving the same requirements. Our experts will teach you how to use Assertions and Code Coverage for a systematic and comprehensive verification. Our experts will also demonstrate the advantages of component level verification with DO-254 CTS (Compliance Tool Set) ideal to hardware verification of Level A/B DO-254 designs. Play webinar   
DO-254/CTS Recorded Webinars
Efficient Verification of Complex FPGA Designs - with Lattice and Aldec Europe   
Abstract: With the complexity of some FPGA designs now comparable to ASIC, designers are faced with challenging cost, power and functional goals. Leading-edge FPGA designs will now benefit from advanced verification methodologies, but do ASIC-focused EDA vendors offer the best solution? This webinar will explain how Aldec tools are uniquely positioned to efficiently support the verification of complex FPGA designs and how (in combination with the new devices from Lattice) designers can meet their functional, cost and power requirements for complex high volume applications. Play webinar   
Active-HDL Recorded Webinars