Aldec Design and Verification Blog

Trending Articles
See the Future with Impact Analysis
Know the impact of requirements changes before they occur

Imagine if you could look into the future… -  See the impact of requirements changes before they occur. -  Know with certainty which lines of code in an HDL design or testbench file needed to be re-evaluated based on a change request....

Like(0) Comments (0) Read more
Simulate Smarter than a Secret Agent
Learn how features like Plot Window can save your life

In James Bond movies, Agent 007 has some awesome gadgets but never listens to Q’s instruction on how to use them properly. I’ve often wondered what it would be like if Bond actually did learn about the various features of his tools...

Like(0) Comments (0) Read more
Visualizing UVM Environments: Debug Features Deliver a Clearer View
Guest Blog from Srinivasan Venkataramanan of CVC

It is an often-quoted statistic that Functional Verification consumes the lion’s share (40-70%) of ASIC and complex FPGA design projects. A less often stated fact, yet no less true, is the majority of verification cycle time is spent...

Like(2) Comments (0) Read more
For DO-254 Compliance, Hardware Flies Not Simulations
How to Increase Verification Coverage by Test

DO-254 defines 3 types of verification methods: Analysis, Test and Review. In order to satisfy the verification objectives defined in DO-254, applicants must formulate a requirements-based verification plan that employs...

Like(1) Comments (0) Read more
Why Digital Design Students choose Active-HDL™
Mixed-language simulation for VHDL-2008, Verilog and SystemVerilog (Design)

Active-HDL™ STUDENT EDITION is a popular solution for university students looking to enhance their digital design learning experience. A mixed-language simulator that supports VHDL-2008,...

Like(1) Comments (0) Read more
Still managing FPGA requirements with Word and Excel?
Smart tips for safety-critical applications, like DO-254

Smart engineers work smart by using tools that are readily available and that they know how to use.  Wise engineers work wisely by first evaluating the options, analyzing the results and making a strategic decision...

Like(1) Comments (0) Read more
Much has changed in the last 30 years
A New Year’s Reflection from Aldec’s founder and CEO

When I first launched Aldec in 1984, home computers hadn’t quite taken off and innovations such as the compact disk and those oversized, power draining cellphones were still struggling to obtain mass acceptance....

Like(1) Comments (0) Read more
It’s no accident that Aldec offers the best VHDL-2008 support
Tools, Resources and Training for VHDL Users

Here at the Aldec corporate office, we have a sign that reminds us all of our mission in the field of Technology. It reads, ‘To deliver solutions that provide the highest productivity to value ratio;...

Like(1) Comments (0) Read more
HES-DVM™ 2013.11 Delivers Increased Speed and Debugging
Introducing Turbo Mode and HesDebugApi

Aldec recently released HES-DVM 2013.11 which introduces an array of customer-requested new features and improved debugging capabilities, speed, and co-emulation infrastructure....

Like(0) Comments (0) Read more
Effective Communication is Key in Relationships… and ESL Design!
Aldec & Agilent EEsof improve digital/ESL relationship with COMRATE™ engine

COMRATE™, the co-simulation solution developed by Aldec and Agilent is a lot like “couples-therapy” that can help get your digital blocks talking to the rest of your model-based design....

Like(2) Comments (0) Read more