Aldec Design and Verification Blog

With the explosion of both in size and complexity of today’s FPGAs and ASICs, methodologies to efficiently manage and control requirements from concept to product rollout have never been more crucial to produce high...

As newer generation FPGAs provide users higher logic capacity for system design, SoC's are concurrently  growing more complex with the integration of high speed serial protocols, multi-core processors, and media interfaces. These SoC designs are pushing the limits of FPGA utilization, and growing...

This year’s Design Automation Conference (DAC) will be held in Austin, Texas.  If we survive the 70% humidity, our team looks forward to meeting you at Booth #2225 from June 3-5. Aldec HQ is located in Nevada just outside of Las Vegas… so we’re accustomed to more of a dry heat....

As we know, the first industry standard trying to solve the Intellectual Property (IP) delivery problem was Verilog-2005. It contained sound theoretical description but lacked some practical usage guidelines needed to create interoperable implementations. VHDL-2008 standard, based on the same donation by...

Modern industrial systems are faced with many key design challenges including: system complexity, real-time performance requirements, evolving standards, and rising costs. ASIC prototyping platforms, such as Aldec HES-7™, provide a platform for designers to implement and verify functionality of...

The most commonly used approach to analyzing objects in an HDL design is based on well-known digital waveforms available with any commercial simulator today. Such a time domain representation of data with respect to time, allows verifying many parameters of a designed digital system, but it may not be efficient for...

Levels A and B airborne hardware are critical to the safety of the aircraft and its passengers.  For both Levels A and B hardware the FAA recommends that designers follow an appropriate design assurance method described in RTCA/DO-254 Appendix B. Elemental Analysis is one of them and it is the most commonly used...

Many experienced Verilog users tend to ignore SystemVerilog - mainly because high-end verification features of the new language are getting the majority of the  attention in the press, and at conferences and trade shows. Those users may not realize that there are many SystemVerilog features that are very useful for...

In today's competitive atmosphere, the ability to get up to speed with any tool is critical. Over the years, Aldec has conducted numerous trainings to help engineers increase their productivity by enhancing their knowledge of Active-HDL, Aldec’s FPGA design entry and simulation tool....

Aldec’s University  Program is committed to providing future engineers with world-class tools for their digital system designs and verification methodologies.  These tools are offered at a lower cost to educational facilities who meet the university program requirements. In addition, students...