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Hardware Emulation Solutions

Hardware Emulation Solutions

Aldec Hardware Emulation Solutions is a hybrid verification and validation ecosystem for hardware and software teams developing the latest SoC and ASIC designs. Partnering the latest high-capacity FPGA technology with industry leading co-emulation standards, HES allows for multiple modes of verification and validation including bit-level simulation acceleration, transaction-level emulation, Hardware prototyping, and Virtual Modeling.

Aldec integrates four main elements to provide best in-class hardware emulation solutions.

FPGA Prototyping Hardware – Reuse prototyping boards utilizing the latest Xilinx® Virtex™ 7 FPGAs for hardware emulation up to 96M ASIC gates with scalable backplane. The Aldec HES-7 prototyping platform incorporates 25 Gb/s non-proprietary backplane connectors for high-speed data transmission, up to 16GB of DDR3 memory, PCI-Express connection to host PC, and an array of media interface peripherals.

Design Verification Manager (DVM) – Fully automated and scriptable design environment which facilitates the setup of simulation acceleration, transaction-level emulation, Hardware Prototyping, and Virtual Modeling with FPGA prototyping Hardware. HES-DVM contains features such as ASIC to FPGA conversion, automatic design partitioning, embedded memory mapping, clock conversions and integration to 3rd party tools.

Runtime Interfaces – HES integrates the latest in hardware/software run-time interfaces utilizing the latest co-emulation standards for a complete verification environment.  Virtual models for OS, peripherals, and the latest processors can be connected to the hardware emulator utilizing co-emulation API and a co-simulation interface. Real-time peripherals can be connected via speed adapters allowing verification teams to emulate industry leading protocols within an emulation environment.

Debugging Tools – HES features an array of debugging capabilities such as static & dynamic probes, transactors the for AXI-4 & AHB bus communication, peripherals transactors (I2C, USB, JTAG, and more), breakpoints and triggering, clock stepping/ Run for, Enhanced visibility with Siloti/Verdi integration, On-Chip logic analyzer (SCE-MI, and Xilinx ChipScope Pro implementation), Memory visibility and API, HES API (C/C++), and off-chip debugging connectors.