What’s involved in simulation of a complex SoC FPGA like Versal ACAP? February 08 Aldec @ DAC 2023: Presenting Design Verification Tools and Solutions for FPGAs and SoCs June 26 Riviera-PRO Supports System Simulation of AMD® Versal™ ACAP Designs June 14 The avionics industry’s growing need for TLM May 18 Aldec and Thales to Co-Present at Certification Together International Conference 2023 May 01 View all news
Turbocharge your FPGA Simulation Workflows: Part 1 - High-Performance RTL Simulation Workflow with Vivado and Active-HDL (EU) Mar 21 (Webinar, Online) Turbocharge your FPGA Simulation Workflows: Part 1 - High-Performance RTL Simulation Workflow with Vivado and Active-HDL (US) Mar 21 (Webinar, Online) Let's challenge UVM! Mar 27 (Webinar, Tokyo, Japan ) Turbocharge your FPGA Simulation Workflows: Part 2 - High-Performance RTL Simulation Workflow with Quartus and Active-HDL (US) Mar 28 (Webinar, Online) Turbocharge your FPGA Simulation Workflows: Part 2 - High-Performance RTL Simulation Workflow with Quartus and Active-HDL (EU) Mar 28 (Webinar, Online) View all events
Essential Steps to Simplify VHDL Testbenches Using OSVVM Verifying AXI Interconnects with ALINT-PRO and Riviera-PRO System Simulation of Versal ACAP Designs Ways to run cocotb: Makefiles, cocotb-test, or your custom setup FPGA Design Verification in a Nutshell (Part 3) Advanced Verification Methods View all webinars