FPGA Design

FPGA designs contain hundreds even thousands of files which are maintained in variety of different formats to support HDL and ESL design languages used to implement FPGA designs. Typically each file is modified frequently by a designer or team of designers and the files require processing by multiple tools (HDL simulation, logic synthesis, FPGA place and route implementation engines in additional to designs that require co-simulation with algorithms based on high level languages such as MATLAB or C,C++) in order to bring the design to realization.Aldec delivers solutions that work with plain text, block diagrams, state diagrams, including bi-directional conversion between code to graphics, graphical waveforms and support VHDL, Verilog, SystemC, SystemVerilog and many other team based design and co-simulation methodologies that organizations deploy. Mixed HDL design files can be added, modified, archived, restored, compiled, simulated, synthesized and implemented without leaving one, convenient project management framework. All results of operations on the design sources appear in the same project framework, enabling quick analysis and design realization. All 3rd party tools required to complete the FPGA design can be easily added, selected and configured. This level of flexibility is especially appreciated by design engineers working with mixed HDL languages, multiple FPGA vendor tools and silicon technologies. A single integrated design environment provides the assurance the designer is working with familiar tools independent of the selected FPGA device.

Solutions: Graphical/Text Design EntrySimulation and DebuggingDocumentation HTML/PDFProject Management/Integration Products: Active-HDL FPGA Simulation