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VIP/IP Products

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Category: Type Part Provider Action
CommunicationsIP

BCH Encoder/Decoder (IP-ALBCH)   

The BCH design includes two independent units, an encoder for generation of the BCH code, and decoder for the BCH code decoding. They can be used separately or together.

Aldec
CommunicationsIP

Discrete Cosine Transform (IP-ALDCT)   

IP-ALDCT soft core is the unit to perform the Discrete Cosine Transform (DCT). It performs two-dimensional 8 by 8 point DCT for the period of 64 clock cycles in pipelined mode.

Aldec
CommunicationsIP

Discrete Cosine Transform (IP-ALIDCT)   

IP-ALIDCT soft core is the unit to perform the Inverse Discrete Cosine Transform (IDCT). It performs two-dimensional 8 by 8 point IDCT for the period of 64 clock cycles in pipelined mode.

Aldec
CommunicationsIP

Viterbi Encoder/Decoder (IP-ALViterbi)   

Viterbi encoding is widely used for satellite and other noisy communications channels.
There are two important components of a channel using Viterbi encoding:

  • the Viterbi encoder (at the transmitter),
  • the Viterbi decoder (at the receiver).

A Viterbi encoder adds extra information in the transmitted signal to reduce the probability of errors in the received signal that may be corrupted by noise.
A Viterbi decoder performs a maximum likelihood detection of 1 bit data transmitted over a channel with inter-symbol interference (ISI). The 1-bit data to be transmitted is encoded with an n-bit convolutional code in the convolutional encoder.

Aldec
CommunicationsIP

DVB-C2 LDPC/BCH Decoder   

DVB-C2 (Digital Video Broadcast - Cable 2nd Generation) is an ETSI standard of the second generation for digital data transmission via cable networks. It complements the existing standards DVB-S2 and DVB-T2 for satellite and terrestrial communication and offers a capacityapproaching coding scheme. The Creonic DVB-C2 IP core integrates the forward error correction as defined by the standard (including LDPC and BCH decoder). It furthermore includes additional signal processing before and after forward error correction (soft-decision demapping, deinterleaving, descrambling).

Creonic GmbH
CommunicationsIP

DVB-RCS Turbo Decoder   

DVB-RCS (Digital Video Broadcast - Interaction channel for satellite distribution systems) is an established ETSI standard for digital data transmission via satellites. It uses a 8-state double-binary turbo decoder that has an excellent error correction performance. This outstanding performance of the DVB-RCS turbo decoder makes it the ideal candidate for further applications where high spectral efficiency is key for lowering costs.

Creonic GmbH
CommunicationsIP

DVB-RCS2 Turbo Decoder   

DVB-RCS2 (Digital Video Broadcast - Second Generation DVB Interactive Satellite System) is the latest ETSI standard of the second generation for digital data transmission via satellites. It uses a new 16-state doublebinary turbo decoder that significantly outperforms its dated 8-state counterpart of DVB-RCS. DVB-RCS2 is the first standard to adopt these highest performance turbo codes. New modulation schemes (8-PSK and 16-QAM) help to increase spectral efficiency even further. The outstanding error correction performance of the DVB-RCS2 turbo decoder makes it the ideal candidate for further applications where high spectral efficiency is key for lowering costs.

Creonic GmbH
CommunicationsIP

DVB-S2 LDPC/BCH Encoder and Decoder   

DVB-S2 (Digital Video Broadcast - Satellite 2nd Generation) is an ETSI standard of the second generation for digital data transmission via satellites. It was published in 2005, being the first standard of the second generation DVB standards (DVB-S2/-T2/-C2). Because of its capacity-approaching forward error correction, today DVB-S2 is the de-facto standard in satellite communication and other applications. The Creonic DVB-S2 IP core integrates the forward error correction as defined by the standard (including LDPC and BCH decoder).

Creonic GmbH
CommunicationsIP

GEO-Mobile Radio LDPC Decoder   

GEO-Mobile Radio (GMR) is an ETSI standard for satellite phones. The Creonic GMR Decoder IP core supports the PNB2 burst packets that were added in GMR Release 2 (GMPRS-1) and use LDPC codes for the first time. The same burst modes and LDPC codes are also in GMR Release 3 (GMR-3G). The Creonic GMR LDPC decoder IP core is a field-proven solution.

Creonic GmbH
CommunicationsIP

IEEE 802.11n LDPC Decoder   

The WiFi family of standards (IEEE 802.11) is used for Wireless Local Area Networks (WLANs). Its first version from 1997 has been extended by many amandments such as IEEE 802.11n-2009 (now part of IEEE 802.11-2012). This amendment was developed in particular for high throughputs of 600 Mbit/s on the air interface. The standard uses convolutional codes for forward error correction as minimum requirement. LDPC codes are optional but because of their superiority over convolutional codes they are widely used today.

The Creonic IEEE 802.11 LDPC decoder is a high performance implementation for WLAN and further applications and supports all LDPC codes as defined by the standard.

Creonic GmbH
CommunicationsIP

IEEE 802.15.3c LDPC Decoder   

The IEEE 802.15 working group specifies standards targeting the wireless personal area network (WPAN). Task group 3 of the working group focuses on high data rates within WPAN. The task group 3c defined a new millimeter-wave-based alternative physical layer (PHY) for the IEEE 802.15.3-2003 standard. This standard (IEEE 802.15.3c-2009) operates at 60 GHz and offers data rates of multiple Gbit/s for applications such as high speed internet access or streaming content download. The task group adopted LDPC codes for these high data rate modes within the single carrier (SC) mode and the high speed interface (HSI) mode.

The Creonic IEEE 802.15.3c LDPC Decoder IP supports all LDPC codes with a codeword size of 672 bits as defined by the standard.

Creonic GmbH
CommunicationsIP

MMSE MIMO Detector   

MIMO (Multiple Input Multiple Output) techniques are being used more and more in recent and upcoming standards since they drastically outperform traditional SISO (Single Input Single Output) techniques in terms of maximum throughput and range. This gain results from an increased spectral efficiency, lowering the overall system costs.

A Minimum Mean Square Error (MMSE) MIMO detector is an integral part of a MIMO receiver. The Creonic MMSE detector offers high throughputs even on low-cost FPGAs and convinces with a low implementation complexity at the same time. Its flexibility at design-time and run-time makes it the ideal fit for all kinds of MIMO applications.

Creonic GmbH
CommunicationsIP

WiMedia 1.5 UWB LDPC Decoder   

The WiMedia UWB standard was developed by the Wi-Media Alliance. Version 1.5 of the standard introduces high payload throughputs of up to 1 Gbit/s for short range communication. LDPC codes have been adopted for these high data rate modes, while convolutional codes are used for the low data rate modes. The Creonic WiMedia 1.5 LDPC Encoder and Decoder IP core supports all LDPC coding schemes as defined by the standard.

Creonic GmbH
CommunicationsIP

Serial FPDP IP Core (VITA 17.1-2003)   

Serial Front Panel Data Port is an industry standard, low-overhead, low-latency, high speed serial communications protocol. sFPDP is ideal for use in applications such as high-speed communication system backplanes, high-bandwidth remote sensor systems, signal processing, data recording, and high-bandwidth video systems. The simple and lightweight nature of the protocol makes it an attractive choice for replacement of parallel bus interconnects using serial transceiver technology. sFPDP can be used in point-topoint or loop topologies, uni-directional or bidirectional links, and easily supports different types of data with efficient and flexible data framing options.

StreamDSP
ControllerIP

AXI DMA Back-End Core   

The Northwest Logic AXI DMA Back-End Core provides highperformance, scatter-gather DMA operation in a flexible fashion. This enables the core to be easily integrated and used in a wide variety of DMA-based systems.

Northwest Logic
ControllerIP

CSI-2 Controller Core   

The CSI-2 Controller Core is part of Northwest Logic’s MIPI Solution. This solution is designed to achieve maximum MIPI throughput while being easy to use.

Northwest Logic
ControllerIP

DMA Back-End Core   

The Northwest Logic DMA Back-End Core provides highperformance, scatter-gather DMA operation in a flexible fashion. This enables the core to be easily integrated and used in a wide variety of DMA-based systems.

Northwest Logic
ControllerIP

Double Data Rate (DDR) SDRAM Controller Core   

Northwest Logic’s Double Data Rate (DDR) SDRAM Controller Core is designed for use in applications requiring high memory throughput, high clock rates and full programmability.

Northwest Logic
ControllerIP

Double Data Rate 2 (DDR2) SDRAM Controller Core   

Northwest Logic’s Double Data Rate 2 (DDR2) SDRAM Controller Core is designed for use in applications requiring high memory throughput, high clock rates and full programmability.

Northwest Logic
ControllerIP

Double Data Rate 3 (DDR3) SDRAM Controller Core   

Northwest Logic’s Double Data Rate 3 (DDR3) SDRAM Controller Core is designed for use in applications requiring high memory throughput, high clock rates and full programmability.

Northwest Logic
ControllerIP

Double Data Rate 4 (DDR4) SDRAM ControllerCore   

Northwest Logic’s Double Data Rate 4 (DDR4) SDRAM ControllerCore is designed for use in applications requiring high memory throughput, high clock rates and full programmability.

Northwest Logic
ControllerIP

DSI Controller Core   

The DSI Controller Core is part of Northwest Logic’s MIPI Solution. This solution is designed to achieve maximum MIPI throughput while being easy to use.

Northwest Logic
ControllerIP

Expresso 3.0   

The Expresso 3.0 Core is part of Northwest Logic’s PCI Express Solution. This solution is designed to achieve maximum PCI Express throughput while being easy to use.

Northwest Logic
ControllerIP

High Bandwidth Memory (HBM) DRAM Controller Core   

Northwest Logic’s High Bandwidth Memory (HBM) DRAM Controller Core is designed for use in applications requiring high memory throughput, high clock rates and full programmability.

Northwest Logic
ControllerIP

Logic Expresso DMA Core   

The Northwest Logic Expresso DMA Core provides highperformance, scatter-gather DMA operation in a flexible fashion. This enables the core to be easily integrated and used in a wide variety of DMA-based systems.

Northwest Logic
ControllerIP

Low Power Double Data Rate 2 (LPDDR2) SDRAM Controller Core   

Northwest Logic’s Low Power Double Data Rate 2 (LPDDR2) SDRAM Controller Core is designed for use in applications requiring high memory throughput, high clock rates and full programmability.

Northwest Logic
ControllerIP

Low Power Double Data Rate 3 (LPDDR3) SDRAM Controller Core   

Northwest Logic’s Low Power Double Data Rate 3 (LPDDR3) SDRAM Controller Core is designed for use in applications requiring high memory throughput, high clock rates and full programmability.

Northwest Logic
ControllerIP

Low Power Double Data Rate 4 (LPDDR4) SDRAM Controller Core   

Northwest Logic’s Low Power Double Data Rate 4 (LPDDR4) SDRAM Controller Core is designed for use in applications requiring high memory throughput, high clock rates and full programmability.

Northwest Logic
ControllerIP

Mobile Double Data Rate (DDR) SDRAM Controller Core   

Northwest Logic’s Mobile Double Data Rate (DDR) SDRAM Controller Core is designed for use in applications requirin high memory throughput, high clock rates and full programmability.

Northwest Logic
ControllerIP

MRAM Controller Core   

Northwest Logic’s MRAM Controller Core is designed for use in applications requiring high memory throughput, high clock rates and full programmability. It fully supports the extended timing requirements of MRAM

Northwest Logic
ControllerIP

Reduced Latency DRAM (RLDRAM) 3 Controller Core   

Northwest Logic’s Reduced Latency DRAM (RLDRAM) 3 Controller Core is designed for use in applications requiring high memory throughput, high clock rates and full programmability.

Northwest Logic
ControllerIP

Reduced Latency DRAM (RLDRAM) II Controller Core   

Northwest Logic’s Reduced Latency DRAM (RLDRAM) II Controller Core is designed for use in applications requiring high memory throughput, high clock rates and full programmability.

Northwest Logic
Data CompressionIP

Helion LZRW3 Loss-less Data Compression cores   

Highly capable loss-less data compression and expansion cores capable of >1Gbps throughputs in FPGA without any requirement for external RAM.

Helion Technology Limited
EncryptionIP

DES Encryption and Decryption Processor (IP-ALDES)   

The IP-ALDES core is the VHDL model of the processor, that performs DES encryption and decryption. The model is fully compliant with FIPS46-2.

Aldec
EncryptionIP

SHA-1 Hash Function Calculation (IP-ALSHA)   

The ALSHA core is the VHDL model of the processor that performs SHA-1 hash function calculation. The model is fully compliant with FIPS180-1.

Aldec
EncryptionIP

Helion AES-CCM combined encryption and authentication cores   

Easy to use and highly integrated AES-CCM cores offering combined encryption and data authentication in a single engine.  Compliant with standards like 802.11, 802.15, 802.16, Zigbee, IEEE1619.1.

Helion Technology Limited
EncryptionIP

Helion AES-GCM combined encryption and authentication cores   

Easy to use and highly integrated AES-GCM cores offering combined encryption and data authentication in a single engine.  Compliant with standards like IPsec,

Helion Technology Limited
EncryptionIP

Helion AES Key Unwrap cores   

Easy to use and highly integrated AES Key Unwrap core, implementing the NIST AES Key Unwrap algorithm and AESKW mode of ANS X9.102.

Helion Technology Limited
EncryptionIP

Helion AES Key Wrap cores   

Easy to use and highly integrated AES Key Wrap core, implementing the NIST AES Key Wrap algorithm and AESKW mode of ANS X9.102.

Helion Technology Limited
EncryptionIP

Helion ANSI Pseudo Random Number Generator (PRNG) cores   

Cryptographic Pseudo Random Number Generator which implements ANSI X9.17 and X9.31 PRNGs based on either Triple-DES or AES encryption algorithms.

Helion Technology Limited
EncryptionIP

Helion DES and 3DES cores   

Easy to use block cipher core which implements DES and Triple-DES encryption and decryption to NIST FIPS publication 46-3.

Helion Technology Limited
EncryptionIP

Helion DVB Common Scrambling Algorithm (CSA) cores   

Easy to use CSA core implements ETSI specified DVB Common Scrambling Algorithm which is ideal for use in BISS-E and BISS Mode-1 Digital Satellite News Gathering applications.

Helion Technology Limited
EncryptionIP

Helion Fast AES encryption and decryption cores   

Low latency, high data rate AES (Advanced Encryption Standard) encryption and decryption IP cores supporting 128, 192 and 256-bit key sizes.

Helion Technology Limited
EncryptionIP

Helion Fast Hashing cores   

Easy to use Fast Hashing cores supporting the MD5, SHA-1, SHA-256, SHA-384 and SHA-512 hashing algorithms, aimed at high data rate applications.

Helion Technology Limited
EncryptionIP

Helion Modular Exponentiation (RSA & Diffie-Hellman) cores   

Easy to use core which implements the Z = YE mod M, the Modular Exponentiation function commonly used in Public-Key Cryptography and ideal for hardware acceleration of RSA, Diffie-Hellman and DSA.

Helion Technology Limited
EncryptionIP

Helion Multi-Mode Tiny Hashing cores   

Super compact multi-mode Hashing core supporting the MD5, SHA-1, SHA-224, SHA-256, SHA-384 and SHA-512 hashing algorithms, each with optional HMAC, aimed at low rate applications.

Helion Technology Limited
EncryptionIP

Helion Standard AES encryption and decryption cores   

Compact, mid data rate AES (Advanced Encryption Standard) encryption and decryption IP cores supporting 128, 192 and 256-bit key sizes.

Helion Technology Limited
EncryptionIP

Helion Tiny AES encryption and decryption cores   

Ultra low area, low data rate AES (Advanced Encryption Standard) encryption and decryption IP cores supporting 128, 192 and 256-bit key sizes.

Helion Technology Limited
Microprocessors and MicrocontrollersIP

Instruction Set Compatible with the 8051 8-bit Microcontroller Architecture (IP-AL8051S)   

IP-AL8051S soft core is instruction set compatible with the 8051 8-bit microcontroller architecture and can achieve average performance of up to 20 million instructions per second.

Aldec
Microprocessors and MicrocontrollersIP

Instruction Set Compatible with the 8052 8-bit Microcontroller Architecture (IP-AL8052S)   

IP-AL8052S soft core is instruction set compatible with the 8052 8-bit microcontroller architecture and can achieve average performance of up to 20 million instructions per second.

Aldec
Microprocessors and MicrocontrollersIP

Intel™ 8051 8-bit Microcontroller (IP-AL8051)   

The IP-AL8051 core is the VHDL model of the Intel™ 8-bit 8051 micro controller. The model is fully compatible with the Intel 8051 standard.

Aldec
Microprocessors and MicrocontrollersIP

Microchip Technology™ PIC16C5x 8-bit micro controller (IP-AL16C5x)   

The IP-AL16C5x core is the VHDL model of the Microchip Technology™ PIC16C5x 8-bit micro controller. The PIC16C5x is a family of 8-bit, ROM based micro controllers with a RISC architecture inside.

Aldec
Peripherals and InterfacesIP

Fast Fourier Transform (IP-ALFFT)   

IP-ALFFT soft core is the unit to perform the Fast Fourier Transform (FFT). It performs one dimensional N -point radix two FFT, where N = 16, 32, 64, 128, 256, 512, 1024, 2048. The data and coefficient widths are tunable in the range 8 to 16.

Aldec
Peripherals and InterfacesIP

Intel™ 8243 Input/Output Expander (IP-AL8243)   

The IP-AL8243 core is the VHDL model of the Intel™ 8243 input/output expander.

Aldec
Peripherals and InterfacesIP

Intel™ 8253 Programmable Counter/Timer Device (IP-AL8253)   

The IP-AL8253 core is the VHDL model of the Intel™ programmable counter/timer device designed for use as an Intel microcomputer peripheral.

Aldec
Peripherals and InterfacesIP

Intel™ 8254 Programmable Counter/Timer Device (IP-AL8254)   

The IP-AL8254 core is the VHDL model of the Intel™ programmable counter/timer device designed for use as an Intel microcomputer peripheral.

Aldec
Peripherals and InterfacesIP

Intel™ 8279 Programmable Keyboard/Display Interface Device (IP-AL8279)   

The AL8279 core is the VHDL model of the Intel™ 8279 Programmable Keyboard/Display Interface device designed for use with Intel microprocessors. The keyboard portion provides a scanned interface to 64-contact key matrix while the display portion provides an interface for popular display technologies (e.g. LED).

Aldec
Peripherals and InterfacesIP

Intel™ Programmable Interrupt Controller (IP-AL8259)   

The AL8259 core is the VHDL model of the Intel™ 8259 Programmable Interrupt Controller used in Intel microprocessor systems to control and prioritize interrupts. It handles up to eight vectored priority interrupts for the CPU. It is cascadable for up to 64 vectored priority interrupts without additional circuitry.

Aldec
Peripherals and InterfacesIP

USB Function Controller, Fully Compatible with USB 1.1 (IP-ALUSB11)   

USB core is the VHDL model of USB Function Controller, which is fully compatible with the USB 1.1 specification. The core has been optimized for popular FPGA devices and its functionality has been verified in the real hardware.

Aldec
Peripherals and InterfacesIP

USB Function Controller, Fully Compatible with USB 2.0 (IP-ALUSB20)   

USB core is the VHDL model of USB Function Controller, which is fully compatible with the USB 2.0 specification. The core has been optimized for popular FPGA devices and its functionality has been verified in the real hardware.

Aldec
Peripherals and InterfacesIP

Genie-AHB Verification IP   

The Genie-AHB Verification IP is a comprehensive verification solution for pre-silicon functional verification of AMBA AHB based designs. It provides a fast and easy solution to verify the AMBA AHB functionality in any FPGA, SoC or ASIC design.

PerfectVIPs
Peripherals and InterfacesIP

Genie-APB Verification IP   

The Genie-APB Verification IP is a comprehensive verification solution for pre-silicon functional verification of AMBA APB based designs. It provides a fast and easy solution to verify the AMBA APB functionality in any FPGA, SoC or ASIC design.

PerfectVIPs
Peripherals and InterfacesIP

Genie-ETH Verification IP   

The Genie-ETH Verification Products are the industry’s most comprehensive verification solution for Ethernet based designs.

PerfectVIPs
Peripherals and InterfacesIP

Genie-NVMe™ Verification IP   

The Genie-NVMe™ Verification IP Products provide the most robust verification solution for NVMe 1.0 based designs. The intelligent Verification Engine, developed with latest technology UVM to reduce design risk, verification time and project costs. Genie-NVMe™ Verification IP can be plugged with PCIe and also plugged with other Interface or Bus.

PerfectVIPs
Peripherals and InterfacesIP

Genie-ONFi Verification IP   

The Genie-ONFi Verification IP most complete verification solution for Open NAND Flash Interface (ONFi) based designs. The intelligent Verification Engine, advanced Comprehensive Test Suite combination of tools to reduce design risk, verification time and project costs.

PerfectVIPs
Peripherals and InterfacesIP

Genie-PCIe2™ Verification IP   

The Genie-PCIe2™ Verification IP based designs. The intelligent Compliance Suite provide the Perfect combination of tools to reduce design risk, verification time and project costs. Genie-PCIe

PerfectVIPs
Peripherals and InterfacesIP

Genie-PCIe™ Verification IP   

The Genie-PCIe™ Verification IP Products provide the most robust verification solution for PCIe 3.0 based designs.

PerfectVIPs
Peripherals and InterfacesIP

Genie-SAS™ Verification IP   

The Genie-SAS™ Verification IP Products are the industry’s most comprehensive verification solution for SAS based designs.

PerfectVIPs
Peripherals and InterfacesIP

Genie-SATA™ Verification IP   

Genie-SATA™ Verification Products are the industry’s most comprehensive verification solution for SATA based designs.

PerfectVIPs
Peripherals and InterfacesIP

Genie-SR-IOV Verification IP   

SR-IOV provides a mechanism by which a Single Root Function (for example a single Ethernet Port) can appear to be multiple separate physical devices. A SR-IOV-capable device can be configured (usually by the VMM/PCIM) to appear in the PCI configuration space as multiple functions, each with its own configuration space complete with Base Address Registers (BARs). The VMM assigns one or more VFs to a VM by mapping the actual configuration space the VFs to the configuration space presented to the virtual machine by the VMM/PCIM.

PerfectVIPs
Peripherals and InterfacesIP

Genie-SSU USB 3.0 Verification IP   

The Genie-SSU USB 3.0 Verification IP Products are the industry’s most advanced verification solution for USB 3.0 based designs.

PerfectVIPs
Peripherals and InterfacesIP

Genie-UAS UA Verification IP   

The Genie-UAS UAS industry’s most advanced verification solution for U designs.

PerfectVIPs
Peripherals and InterfacesIP

Genie-USB Verification IP   

The Genie-USB Verification IP Products are the industry’s most advanced verification solution for USB 2.0 based designs.

PerfectVIPs
Peripherals and InterfacesIP

Genie-XP Verification IP   

The Genie-XP Verification IP Product is the industry’s most comprehensive verification solution for SAS based designs.

PerfectVIPs
Peripherals and InterfacesIP

The Genie-FC™ Verification IP   

The Genie-FC™ Verification IP FC based designs. Its intelligent comprehensive Compliance Suite success.

PerfectVIPs