VIP/IP Products

The BCH design includes two independent units, an encoder for generation of the BCH code, and decoder for the BCH code decoding. They can be used separately or together.

IP-ALDCT soft core is the unit to perform the Discrete Cosine Transform (DCT). It performs two-dimensional 8 by 8 point DCT for the period of 64 clock cycles in pipelined mode.

IP-ALIDCT soft core is the unit to perform the Inverse Discrete Cosine Transform (IDCT). It performs two-dimensional 8 by 8 point IDCT for the period of 64 clock cycles in pipelined mode.

Viterbi encoding is widely used for satellite and other noisy communications channels.
There are two important components of a channel using Viterbi encoding:

• the Viterbi encoder (at the transmitter),
• the Viterbi decoder (at the receiver).

A Viterbi encoder adds extra information in the transmitted signal to reduce the probability of errors in the received signal that may be corrupted by noise.
A Viterbi decoder performs a maximum likelihood detection of 1 bit data transmitted over a channel with inter-symbol interference (ISI). The 1-bit data to be transmitted is encoded with an n-bit convolutional code in the convolutional encoder.

DVB-C2 (Digital Video Broadcast - Cable 2nd Generation) is an ETSI standard of the second generation for digital data transmission via cable networks. It complements the existing standards DVB-S2 and DVB-T2 for satellite and terrestrial communication and offers a capacityapproaching coding scheme. The Creonic DVB-C2 IP core integrates the forward error correction as defined by the standard (including LDPC and BCH decoder). It furthermore includes additional signal processing before and after forward error correction (soft-decision demapping, deinterleaving, descrambling).

DVB-RCS2 (Digital Video Broadcast - Second Generation DVB Interactive Satellite System) is the latest ETSI standard of the second generation for digital data transmission via satellites. It uses a new 16-state doublebinary turbo decoder that significantly outperforms its dated 8-state counterpart of DVB-RCS. DVB-RCS2 is the first standard to adopt these highest performance turbo codes. New modulation schemes (8-PSK and 16-QAM) help to increase spectral efficiency even further. The outstanding error correction performance of the DVB-RCS2 turbo decoder makes it the ideal candidate for further applications where high spectral efficiency is key for lowering costs.

DVB-S2 (Digital Video Broadcast - Satellite 2nd Generation) is an ETSI standard of the second generation for digital data transmission via satellites. It was published in 2005, being the first standard of the second generation DVB standards (DVB-S2/-T2/-C2). Because of its capacity-approaching forward error correction, today DVB-S2 is the de-facto standard in satellite communication and other applications. The Creonic DVB-S2 IP core integrates the forward error correction as defined by the standard (including LDPC and BCH decoder).

GEO-Mobile Radio (GMR) is an ETSI standard for satellite phones. The Creonic GMR Decoder IP core supports the PNB2 burst packets that were added in GMR Release 2 (GMPRS-1) and use LDPC codes for the first time. The same burst modes and LDPC codes are also in GMR Release 3 (GMR-3G). The Creonic GMR LDPC decoder IP core is a field-proven solution.

The WiFi family of standards (IEEE 802.11) is used for Wireless Local Area Networks (WLANs). Its first version from 1997 has been extended by many amandments such as IEEE 802.11n-2009 (now part of IEEE 802.11-2012). This amendment was developed in particular for high throughputs of 600 Mbit/s on the air interface. The standard uses convolutional codes for forward error correction as minimum requirement. LDPC codes are optional but because of their superiority over convolutional codes they are widely used today.

The Creonic IEEE 802.11 LDPC decoder is a high performance implementation for WLAN and further applications and supports all LDPC codes as defined by the standard.

The IEEE 802.15 working group specifies standards targeting the wireless personal area network (WPAN). Task group 3 of the working group focuses on high data rates within WPAN. The task group 3c defined a new millimeter-wave-based alternative physical layer (PHY) for the IEEE 802.15.3-2003 standard. This standard (IEEE 802.15.3c-2009) operates at 60 GHz and offers data rates of multiple Gbit/s for applications such as high speed internet access or streaming content download. The task group adopted LDPC codes for these high data rate modes within the single carrier (SC) mode and the high speed interface (HSI) mode.

The Creonic IEEE 802.15.3c LDPC Decoder IP supports all LDPC codes with a codeword size of 672 bits as defined by the standard.

MIMO (Multiple Input Multiple Output) techniques are being used more and more in recent and upcoming standards since they drastically outperform traditional SISO (Single Input Single Output) techniques in terms of maximum throughput and range. This gain results from an increased spectral efficiency, lowering the overall system costs.

A Minimum Mean Square Error (MMSE) MIMO detector is an integral part of a MIMO receiver. The Creonic MMSE detector offers high throughputs even on low-cost FPGAs and convinces with a low implementation complexity at the same time. Its flexibility at design-time and run-time makes it the ideal fit for all kinds of MIMO applications.

The WiMedia UWB standard was developed by the Wi-Media Alliance. Version 1.5 of the standard introduces high payload throughputs of up to 1 Gbit/s for short range communication. LDPC codes have been adopted for these high data rate modes, while convolutional codes are used for the low data rate modes. The Creonic WiMedia 1.5 LDPC Encoder and Decoder IP core supports all LDPC coding schemes as defined by the standard.

Serial Front Panel Data Port is an industry standard, low-overhead, low-latency, high speed serial communications protocol. sFPDP is ideal for use in applications such as high-speed communication system backplanes, high-bandwidth remote sensor systems, signal processing, data recording, and high-bandwidth video systems. The simple and lightweight nature of the protocol makes it an attractive choice for replacement of parallel bus interconnects using serial transceiver technology. sFPDP can be used in point-topoint or loop topologies, uni-directional or bidirectional links, and easily supports different types of data with efficient and flexible data framing options.

Highly capable loss-less data compression and expansion cores capable of >1Gbps throughputs in FPGA without any requirement for external RAM.

The IP-ALDES core is the VHDL model of the processor, that performs DES encryption and decryption. The model is fully compliant with FIPS46-2.

The ALSHA core is the VHDL model of the processor that performs SHA-1 hash function calculation. The model is fully compliant with FIPS180-1.

Easy to use and highly integrated AES-CCM cores offering combined encryption and data authentication in a single engine.  Compliant with standards like 802.11, 802.15, 802.16, Zigbee, IEEE1619.1.

Easy to use and highly integrated AES-GCM cores offering combined encryption and data authentication in a single engine.  Compliant with standards like IPsec,

Easy to use and highly integrated AES Key Unwrap core, implementing the NIST AES Key Unwrap algorithm and AESKW mode of ANS X9.102.

Easy to use and highly integrated AES Key Wrap core, implementing the NIST AES Key Wrap algorithm and AESKW mode of ANS X9.102.

Cryptographic Pseudo Random Number Generator which implements ANSI X9.17 and X9.31 PRNGs based on either Triple-DES or AES encryption algorithms.

Easy to use block cipher core which implements DES and Triple-DES encryption and decryption to NIST FIPS publication 46-3.

Easy to use CSA core implements ETSI specified DVB Common Scrambling Algorithm which is ideal for use in BISS-E and BISS Mode-1 Digital Satellite News Gathering applications.

Low latency, high data rate AES (Advanced Encryption Standard) encryption and decryption IP cores supporting 128, 192 and 256-bit key sizes.

Easy to use Fast Hashing cores supporting the MD5, SHA-1, SHA-256, SHA-384 and SHA-512 hashing algorithms, aimed at high data rate applications.

Easy to use core which implements the Z = Y^E mod M, the Modular Exponentiation function commonly used in Public-Key Cryptography and ideal for hardware acceleration of RSA, Diffie-Hellman and DSA.

Super compact multi-mode Hashing core supporting the MD5, SHA-1, SHA-224, SHA-256, SHA-384 and SHA-512 hashing algorithms, each with optional HMAC, aimed at low rate applications.

Compact, mid data rate AES (Advanced Encryption Standard) encryption and decryption IP cores supporting 128, 192 and 256-bit key sizes.

Ultra low area, low data rate AES (Advanced Encryption Standard) encryption and decryption IP cores supporting 128, 192 and 256-bit key sizes.

IP-AL8051S soft core is instruction set compatible with the 8051 8-bit microcontroller architecture and can achieve average performance of up to 20 million instructions per second.

IP-AL8052S soft core is instruction set compatible with the 8052 8-bit microcontroller architecture and can achieve average performance of up to 20 million instructions per second.

The IP-AL8051 core is the VHDL model of the Intel™ 8-bit 8051 micro controller. The model is fully compatible with the Intel 8051 standard.

The IP-AL16C5x core is the VHDL model of the Microchip Technology™ PIC16C5x 8-bit micro controller. The PIC16C5x is a family of 8-bit, ROM based micro controllers with a RISC architecture inside.

IP-ALFFT soft core is the unit to perform the Fast Fourier Transform (FFT). It performs one dimensional N -point radix two FFT, where N = 16, 32, 64, 128, 256, 512, 1024, 2048. The data and coefficient widths are tunable in the range 8 to 16.

The IP-AL8243 core is the VHDL model of the Intel™ 8243 input/output expander.

The IP-AL8253 core is the VHDL model of the Intel™ programmable counter/timer device designed for use as an Intel microcomputer peripheral.

The IP-AL8254 core is the VHDL model of the Intel™ programmable counter/timer device designed for use as an Intel microcomputer peripheral.

The AL8279 core is the VHDL model of the Intel™ 8279 Programmable Keyboard/Display Interface device designed for use with Intel microprocessors. The keyboard portion provides a scanned interface to 64-contact key matrix while the display portion provides an interface for popular display technologies (e.g. LED).

The AL8259 core is the VHDL model of the Intel™ 8259 Programmable Interrupt Controller used in Intel microprocessor systems to control and prioritize interrupts. It handles up to eight vectored priority interrupts for the CPU. It is cascadable for up to 64 vectored priority interrupts without additional circuitry.

USB core is the VHDL model of USB Function Controller, which is fully compatible with the USB 1.1 specification. The core has been optimized for popular FPGA devices and its functionality has been verified in the real hardware.

USB core is the VHDL model of USB Function Controller, which is fully compatible with the USB 2.0 specification. The core has been optimized for popular FPGA devices and its functionality has been verified in the real hardware.