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Name Products Type Action
39 results (page 1/2)
Accelerate SoC Simulation Time of Newer Generation FPGAs   
Comprehensive verification that can be provided by HDL simulators is good, but not ideal. What is necessary is a faster, safer, and more thorough verification environment that combines the robustness of an HDL simulator with the speed of FPGA prototyping boards. The goal is to put together the power of these two verification methodologies into one platform.
HES-DVM White Papers
All-in-C Behavioral Synthesis and Verification   
This paper presents the benefits of C language-based behavioral synthesis design methodology over traditional RTL-based methods for System LSI, or SoC designs. A comprehensive C-based tool flow, based on CyberWorkBench®, developed during the last twenty years at NEC’s R&D laboratories is introduced. This includes behavioral synthesis and formal verification and hardware-software co-simulation of entire complex SoC. First we introduce the “All-in-C” concept based on CyberWorkBench. Then we discuss the behavioral synthesis for various types of circuits and examine the advantages of behavioral synthesis on the hand of commercial ICs. We show that currently entire SoCs are created using this flow in a fraction of the time taken by traditional approaches. Behavioral IP and C-based configurable processor synthesis and automatic architecture exploration is explained next. At the end we demonstrate a real world example of a mobile phone SoC where most of the modules are synthesized from C descriptions using CyberWorkBench.
CyberWorkBench White Papers
ARM Cortex SoC Prototyping Platform for Industrial Applications   
Modern industrial systems are faced with many key design challenges including: system complexity, real-time performance requirements, evolving standards, and rising costs. ASIC prototyping platforms, such as the Aldec HES-7, provide a platform for designers to implement and verify functionality of industrial systems at-speed prior to silicon tape-out, saving money from costly re-spins. In this white paper, we take a look how to tackle a few industrial design applications with Aldec’s HES-7, which now supports ARM Cortex-A9 based designs by leveraging Xilinx’s new Zynq All Programmable SoC.
HES-7 White Papers
ASIC Prototyping - co-authored with Xilinx   
This paper highlights possibilities of ASIC verification using FPGA-based prototyping, considering the latest Virtex-7 devices and Aldec HES-7 dual Virtex-7 2000T ASIC prototyping board. In addition, the most common partitioning issues and resolutions are described.
HES-7 White Papers
Automated ASIC Regressions With Aldec Server Farm Manager   
Abstract: Aldec's Server Farm Manager (SFM) addresses ASIC regression testing issues for the fast, cost effective and high quality ASIC design verification.
Active-HDL White Papers
Best Design Practices for High Capacity FPGA Devices   
With the latest FPGA technology advancements and release of large-scale FPGA devices, design teams are facing more challenges than ever in producing high quality HDL code. In order to save time during Functional Verification and Implementation stages, it becomes increasingly important to ensure the quality of design starting from the very early stages of the design process. In an ASIC design flow, a Lint tool (sometime referred to as Design Rule Checkers) ensures early-stage design quality, and maintaining this quality throughout the project lifecycle.
ALINT White Papers
C-based SoC Design Flow and EDA Tools: An ASIC and System Vendor Perspective   
This paper examines the achievements and future of SoC design methodology and design flow from the viewpoints of an in-house EDA team of an ASIC and system vendor. We initially discuss the problems of the design productivity gap caused by the SoC’s complexity and the timing closure caused by deep submicron technology. To solve these two problems, we propose a C-based SoC design environment that features integrated high-level synthesis and verification tools. A high-level synthesis system is introduced using various successful industrial design examples, and its advantages and drawbacks are discussed. We then look at the future directions of this system. The high-level verification environment consists of mixed-level hardware/software co-simulator, formal and semi-formal verifiers, and test-bench generators. The verification tools are tightly integrated with the high-level synthesis system and take advantage of information from the synthesis system. Then, we discuss the possibility of incorporating physical design feature into the C-based SoC design environment. Finally, we describe our global vision for an SoC architecture and SoC design methodology.
CyberWorkBench White Papers
Clarifying Language Methodology Confusion   
Abstract: Engineers working on modern, large FPGA designs face multiple challenges: changing languages, methodologies and tools implementing them. The fact that many designs now contain both hardware and software only adds to the confusion. This document tries to clarify the situation.
Active-HDL White Papers
Concurrent FPGA-PCB Design within an Integrated Design Environment   
The increasing adoption of large, high-pin-count and high-speed FPGA devices means that right-first-time printed circuit board (PCB) design practices are more essential than ever for ensuring correct system operation. Typically, the PCB design takes place concurrently with the design and programming of the FPGA. Signal and pin assignments are initially made by the FPGA designer, and the board designer must correctly transfer these assignments to the symbols used in their system circuit schematics and board layout. As the board design progresses, pin reassignments may be needed to optimize the PCB layout. These reassignments must in turn be relayed back to the FPGA designer so that the new assignments can be processed through updated placement and routing of the FPGA design. To overcome these challenges, Zuken and Aldec provide an integrated design environment to support these design flows.
Active-HDL White Papers
Corporate Standardization of FPGA Design Flow   
Growing customer requirements and technological abilities increase the design complexity of hardware and software. Time to market is shortening as well as the lifetime of new designs. In order to meet all those requirements a new approach to the design process is required.
Active-HDL White Papers
Debugging SCE-MI Co-Emulation in Riviera-PRO   
Abstract: Debugging a design during emulation with a high level of visibility can be a challenge. This paper presents Aldec’s solution to this problem; a debugging environment for SCE-MI co-emulation that provides 100% signal visibility of the design running in an FPGA-based emulator. Debug probes captured intelligently from emulator retain original signals names and hierarchy paths to provide true RTL view of design in emulation.
Active-HDL White Papers
DO-254 Requirements Traceability   
DO-254 enforces a strict requirements-driven process for the development of commercial airborne electronic hardware. For DO-254, requirements must drive the design and verification activities, and requirements traceability helps to ensure this. This paper explains the rationale behind requirements traceability including its purpose and resulting benefits when done correctly.
Spec-TRACER White Papers
DO-254 Tool Qualification Process Guidance for Active-HDL Code Coverage   
The purpose of the document is to Guide the Qualification Process for Active-HDL Code Coverage tool.
DO-254/CTS White Papers
DO-254: Increasing Verification Coverage by Test   
Verification coverage by test is essential to satisfying the objectives of DO-254. However, verification of requirements by test during final board testing is challenging and time-consuming. This white paper explains the reasons behind these challenges, and provides recommendations how to overcome them. The recommendations center around Aldec’s unique device testing methodology that can significantly increase verification coverage by test.
DO-254/CTS White Papers
Embedded Systems Verification   
Abstract: As the number of mobile and personal applications grows, usage of embedded processors becomes a necessity. New FPGA devices with so called soft or hard processor cores enable fast migration from the FPGA-only to the SoC applications and projects. This affects not only the hardware alone, but also the tools supporting the latest FPGA devices for SoC designers. Such tools are discussed within this document.
Active-HDL White Papers
Enhancing Verilog Designs with Embedded PSL   
Abstract: PSL (Property Specification Language) is one of the easiest introductions to the world of design properties, assertions and coverage points to anybody familiar with Verilog HDL. The designer of a digital circuit has the best understanding of the operation of the circuit, which makes her or him the best person to define properties that will fire assertion messages in case of incorrect design behavior during simulation or provide valuable feedback to the testbench creator by showing that all desired behaviors were covered during verification. For this reason, the use of embedded PSL properties and assertions is highly beneficial to the engineers and makes their designs better.
Active-HDL White Papers
Enhancing Verilog Designs with SVA   
Abstract: SVA (SystemVerilog Assertions) language is one of the easiest introductions to the world of design properties, assertions and coverage points to anybody familiar with Verilog HDL. The designer of a digital circuit has the best understanding of the operation of the circuit, which makes her or him the best person to define properties that will fire assertion messages in case of incorrect design behavior during simulation or provide valuable feedback to the testbench creator by showing that all desired behaviors were covered during verification. For this reason, the use of SVA properties and assertions directly in the design code is highly beneficial to the engineers and makes their designs better.
Active-HDL White Papers
Enhancing VHDL Designs with Embedded PSL   
Abstract: PSL (Property Specification Language) is the easiest introduction to the world of design properties, assertions and coverage points to anybody familiar with VHDL (VHSIC Hardware Description Language). The designer of a digital circuit has the best understanding of the operation of the circuit, which makes her or him the best person to define properties that will fire assertion messages in case of incorrect design behavior during simulation or provide valuable feedback to the testbench creator by showing that all desired behaviors were covered during verification. For this reason, the use of embedded PSL properties and assertions is highly beneficial to the engineers and makes their designs better.
Active-HDL White Papers
HDL Simulation And Mathematical Modeling Integration   
Abstract: This paper presents a new approach in domain of high level digital circuits simulation and modeling that benefits from high level mathematical environment delivered by MATLAB. It allows to integrate design process and directly verify obtained results with mathematical formulas or complex operations that are not available in standard HDL languages. A part of HDL code can be placed for verification purposes inside the advanced mathematical model or can execute complex calculation. Paper presents problems that are introduced by hybrid simulation and modeling environment concerning data representation, simulation process and optimal performance.
Active-HDL White Papers
Interoperable IP Delivery   
Abstract: This paper describes the theoretical background, current status and future challenges facing interoperable cryptosystem for safe delivery of Intellectual Property (IP) to be used in VHDL and SystemVerilog design and verification. The system must be reliable, and interoperable, i.e. enable safe use of IP source in a variety of tools. IEEE P1735 Working Group currently develops proposed standard describing such a cryptosystem.
Active-HDL White Papers