| Whitepaper Title | | | Advanced Verification |
| Introducing Transactions In Design Verification | Download |
| Randomization and Functional Coverage in VHDL | Download |
| Assertions and Functional Coverage |
| Deploying Properties Assertions and Coverage | Download |
| Enhancing Verilog Designs with Embedded PSL | Download |
| Enhancing Verilog Designs with SVA | Download |
| Enhancing VHDL Designs with Embedded PSL | Download |
| Design |
| Corporate standardization of FPGA design flow | Download |
| Clarifying Language Methodology Confusion | Download |
| Encryption |
| Interoperable IP Delivery | Download |
| Hardware Emulation Solutions |
| Simulation Acceleration with HES XCELL | Download |
| Debugging SCE-MI Co-Emulation in Riviera-PRO | Download |
| Verification of Ethernet Designs with SCE-MI based Aldec Emulator | Download |
| Virtual Modeling with Aldec and Imperas | Download |
| Meeting Growing Verification Demands | Download |
| Using FPGA Based Simulation Acceleration in Typical ASIC Design Flow | Download |
| Using FPGA Prototyping Board as an SoC Verification and Integration Platform | Download |
| HDL Languages |
| Vector_Implementation_of_Integer_Arithmetic_in_VHDL | Download |
| System Level Design - SystemC Using Transaction Level Modeling | Download |
| Military & Aerospace Verification |
| Design Verification Methodology Aldec DO-254 Compliance Tool Set | Download |
| Superior Approach to DO-254 Hardware Verification | Download |
| Tool Qualification Process Guidance for ActiveHDL Code Coverage | Download |
| Q__A_with_FAA_DO-254_DER_Randall_Fulton | Download |
| Tool Assessment and Qualification with the Aldec DO-254 Compliance Tool Set | Download |
| RTL Simulation & Verification |
| HDL Simulation And Mathematical Modeling Integration | Download |
| Automated ASIC Regressions With Aldec Server Farm Manager | Download |
| Concurrent FPGA-PCB Design within an Integrated Design Environment | Download |
| Embedded Systems Verification | Download |
