Hybrid Verification Platform
HES-DVM™ is a fully automated and scriptable Hybrid Verification and Validation environment for SoC and ASIC designs up to 96M ASIC gates capable of bit-level simulation acceleration, SCE-MI 2.1 transaction emulation, hardware prototyping, and virtual modeling. Utilizing the latest in co-emulation standards, hardware and software design teams are able to have early access to the latest FPGA technology, and work concurrently with one another developing and verifying high-level code with RTL.
HES-DVM provides hardware design teams with multiple modes of high-speed verification and validation including simulation acceleration, transaction level emulation, and hardware prototyping for chip and system level verification of SoC and ASIC systems. Combined powerful debugging tools allowing 100% visibility into the DUT and speed adapters to connect industry standard interfaces to the design environment, verification teams are able to reduce test time and risks of silicon re-spins.
Software Development with Complete OS and Processor Solutions
HES-DVM enables Hardware and Software Co-Verification utilizing a SCE-MI infrastructure which connects TLM modules to the DUT residing in hardware via high-speed AXI and AHB bus transactors. TLM modules can include virtual platforms utilizing the latest embedded processors, peripherals, and complete OS platforms for a complete SoC environment within HES-DVM.
- Bit-Level Simulation Acceleration
- SoC HW/SW Co-Verification
- Transaction Level Emulation with SCE-MI 2.0, SystemC/C/C++, TLM2.0
- Extensive Debugging (static/dynamic probes, memory access using GUI & API)
- Fully Scriptable Environment
- RTL Simulator Interfaces: Active-HDL™, NC-Sim®, ModelSim®, Riviera-PRO™, QuestaSim® and VCS-MX®
- Off-the-shelf FPGA prototyping boards support (Aldec HES-5, Synopsys® HAPS™)
- Custom-in-house FPGA prototyping boards support
- Virtual Modeling with Imperas® OVP™ and OVPsim™
- Linux and Windows® 32/64 bit support