ASIC and Large FPGA Verification
Riviera-PRO is a proven high-performance, mixed-language simulation engine with advanced debugging tools for ASIC and FPGA design teams. Riviera-PRO supports VHDL, Verilog®, SystemVerilog, SystemC, C/C++, PSL and OVA assertions from one common design environment. Riviera-PRO enables mixed RTL debugging, long regression testing, timing simulation and electronic system level (ESL) verification.
Top Features
- Common-Kernel Mixed Language Simulator
- IEEE Standards Support (VHDL, Verilog, SystemVerilog, SystemC)
- Universal HDL/SystemC code level Debugging
- Assertion and Coverage based verification
- DSP/HDL algorithm co-simulation
- Script compatible with other HDL simulators
- Multi-Platform (32/64bit Linux®, Solaris®, Windows®)