Riviera-PRO Configurations

ALDEC simulators provide full support of the IEEE 1076-1993 Standard, IEEE 1076™-2002 VHDL standard and majority of just published IEEE 1076™-2008 Standard.More >>

ALDEC simulators provide full support of the IEEE 1364-2005 Standard. To enable simulation of a large variety of Verilog designs, both legacy and new, ALDEC simulators can be set to work in Verilog ’95, 2001 and 2005 modes.More >>

SystemVerilog is a set of extensions to the Verilog HDL that allow higher level of modeling and efficient verification of large digital systems.More >>

SystemC is an environment that allows description and verification of digital systems using C++. More >>

Riviera-PRO supports SystemVerilog (IEEE Std. 1800™-2009) in three areas: hardware description extensions, assertions and advanced verification.More >>

Verification Libraries (UVM/OVM and VMM)More >>

The HDL Editor is a text editor designed for editing an HDL source code. It is tightly integrated with the compiler and simulator to enable debugging capabilities.More >>

The HDL Editor allows using code autocomplete for all the languages supported by Riviera-PRO. More >>

The Design Manager is a tool that allows you to view and manage workspaces, attached designs and their resources like HDL source files, waveform files, macros, code coverage and profiler results with a single mouse click.More >>

With large number of windows available in Riviera-PRO, keeping all of them open simultaneously is not feasible and frequent reconfiguring of GUI is tedious.More >>

Aldec simulators support several scripting methods varying in the level of abstraction and possible applications. More >>

Simulations can be stopped on a breakpoint. Aldec supports both breakpoints in the source code as well as signal breakpoints.More >>

Active-HDL provides an interactive graphical environment for design code tracing and verification.More >>

The Accelerated Waveform Viewer is a high performance tool for graphical presentation of simulation data stored in a binary simulation database (*.asdb).More >>

The Signal Agent in VHDL allows monitoring and driving VHDL signals from any VHDL block.More >>

Post Simulation Debug is an advanced feature that allows users to observe the simulation results after the simulation has been finished.More >>

In large designs where multiple signals must be observed during simulation, keeping them in one waveform window is inconvenient: since all signals cannot fit in one window, frequent scrolling is required to get to the desired waveform data.More >>

The Compare Waveforms option compares waveforms displayed in the Waveform window with pattern waveforms from a specific waveform file.More >>

The Memory Viewer is a debugging tool that has been designed to display memory objects defined in an active design.More >>

Riviera-PRO allows simultaneous and seamless debugging of pure SystemC designs and mixed HDL-SystemC in a single environment.More >>

Design and verification engineers who implemented assertions and covers in their project can observe their behavior during regular simulation and debugging in multiple windows.More >>

The SWIFT SmartModel Library contains behavioral simulation models of standard integrated circuits.More >>

Riviera-PRO output FSDB files that work with SpringSoft Verdi and legacy Debussy debuggers. Riviera-PRO work with SpringSoft products in post-processing mode(PSD).More >>

X-Trace helps you quickly identify the cause of unexpected values by reporting information on changes from valid to unknown, uninitialized, or user-defined values in the simulated model.More >>

The Advanced Dataflow window is a powerful tool that allows designers to explore the connectivity of an active design and analyze dataflow among instances, concurrent statements, signals, nets, and registers during simulation.More >>

The stand-alone Waveform Viewer can be used to: display simulation results created in previous simulation runs and display simulation results on the fly, while simulation is still in progress.More >>

Most ALDEC simulator configurations support mixed (VHDL and Verilog) designs, but single language (VHDL-only or Verilog-only) configurations are also available.More >>

The Verilog PLI (Programming Language Interface) and VPI (Verilog Procedural Interface) provide a standard mechanism to access and modify data in a simulated Verilog model.More >>

The VHPI interface provides a standard means to access data in VHDL models elaborated in Active-HDL and Riviera-PRO.More >>

DPI, or the Direct Programming Interface, is the next generation interface between SystemVerilog code and foreign C/C++ code.More >>

The VCD (Value Change Dump) file format is specified in the IEEE Std. 1364-1995 standard. The VCD file is an ASCII file containing header information, variable definitions, and variable value changes.More >>

With incremental compilation, small change in one of many design sources does not require recompilation of the entire design. Compilers working in incremental mode can ignore not only files that were not changed, but also areas of larger files that were not modified.More >>

Compilers can utilize newer workstations with multiple processors/processor cores to simultaneously translate different parts of the design, significantly reducing compilation times.More >>

Elaboration is the part of design translation that builds simulation model out of compiled design code and library resources. While required after compilation and before simulation initialization, elaboration separate from those processes can significantly reduce processing time of large designs.More >>

Library protection offers four security levels when compiled models are distributed in the form of library files without releasing their source code.More >>

Using standard design source encryption is a much easier form of managing IP creation and delivery than any kind of binary file encryption. Riviera-PRO supports standard methodology introduced in IEEE Std. 1076-2008. More >>

Using standard design source encryption is a much easier form of managing IP creation and delivery than any kind of binary file encryption. Riviera-PRO supports standard methodology introduced in IEEE Std. 1364-2005. More >>

Aldec simulators support the SecureIP methodology of IP delivery implemented in Xilinx tools.More >>

This option enables Aldec customers with VHDL only license to simulate the most recent Altera Libraries and Megafunctions without purchasing a separate Verilog license (which is required as some of the design units, as well as Megafunctions generated by the MegaWizard™ in Quartus® 11.0, are written in Verilog/SystemVerilog).More >>

Library compatibility across different platforms enables more efficient work of teams working on the same projects, but equipped with different workstations. One set of design libraries can be kept in a convenient location with easy access from all team members.More >>

The ability for the simulator to run at 64-bit bus throughput application speeds and utilize extended memory. (Not applicable on Riviera-PRO LV).More >>

The Verilog RTL & Gate performance optimizer accelerates simulation of all types of Verilog designs, including designs with timing, gate-level designs, and designs with predominantly behavioral code. More >>

Transaction-Level Visual Debugging refers to advanced capability of the Waveform Viewer that enables representing simulation data at a higher level of abstraction. More >>

The Profiler identifies design units or code sections that put the greatest strain on the simulator. This information is valuable for optimizing the simulation environment and improving performance.More >>

Due to the complexity of contemporary designs, there is a need for extensive testing of new products. Server Farm Manager (SFM) shifts the regression paradigm and provides not only simulation technology but also a tool for automatic management of thousands of parallel simulations. More >>

Acceleration speeds up verification by co-simulating HDL code and portions of the design pushed into hardware (mainly well tested blocks or IP blocks). Emulation allows in-hardware simulation and extensive debugging of large systems that will eventually work on different platform.More >>

Code Coverage is a debugging tool that aids the verification process.More >>

Specification of properties and their use in assertions and functional coverage is the essential element of designing modern systems and their verification algorithms.More >>

Functional Coverage can provide information about the quality of the design verification process.More >>

The Simulink Interface simplifies verification of hardware designs by providing robust visualization and analysis toolsets.More >>

Aldec simulators integrate The MathWorks' intuitive MATLAB language and a technical computing environment.More >>

Aldec® ALINT™ analyzes VHDL, Verilog and Mixed Language HDL code during compilation, prior to simulated or synthesized.More >>

ALINT supports new sets of rules that facilitate compliance with DO-254.More >>

STARC® based programmable design and coding guideline checker of complex system-on-chip designs.More >>

Reuse Methodology Manual (RMM) design rule library is based on the industry-proven manual from Synopsys Inc. and Mentor Graphics Corp. which defines the methodology for effective design reuse and verification.More >>

The network floating configuration (multiple users) is based on a license started on a remote machine (license server) running on the Windows or Linux platform.More >>

One Year Time Based License (TBL) grants a designer a license to use the product for a period of one year. A 1 year support contract is included with the purchase of TBL license.More >>

A perpetual license is a license with no expiration date. A 1 year support contract is included with the purchase of perpetual license.More >>

Linux x86/x86_64 support.More >>

Builds are tested on all the latest platforms, including Windows 7, to ensure correct operation on users' workstations.More >>