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Configurations
Active-HDL 8.1 Configurations (Feature Matrix)
Display Movies
Active-HDL 8.1
Features
Movies
x
Desktop Master (DM)
x
Designer Edition
x
Plus Edition (PE)
x
Expert Edition (EE)
Design Entry
HDL, Text, Block Diagram and State Machine Editor
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Language assistant with templates and auto-complete
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Hierarchy Viewer with Configurations Support
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Macro, Tcl/TK, Perl script support
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Pre-compiled FPGA Vendor Libraries
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Code2Graphics™ Converter
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Legacy Schematic Design Import and Symbol Import/Export
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Supported Languages
Single or Mixed Language
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VHDL IEEE 1076 (1987, 1993, 2002 and 2008)
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Verilog® HDL IEEE 1364 (1995, 2001 and 2005)
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SystemVerilog IEEE 1800 (Design)
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Verilog Programming Language Interface (PLI/VPI)
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VHDL Programming Language Interface (VHPI)
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EDIF 2 0 0
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Language Interface Wizard (PLI/VPI/VHPI/DPI)
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SystemVerilog IEEE DPI w/Wizard
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SystemC™ 2.2 IEEE 1666/OSCI 2.2/TLM 2.0
Option
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Code Generation Tools
IP Core Component Generator
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VHPI/PLI/VPI, SystemC Transactor and New File Wizards
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Testbench Generation from Waveforms
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Testbench Generation from State Diagram
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Project Management
Design Flow Manager for All FPGA Vendors
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Revision Control Interface
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Workspace and Design Archiving
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Support for Multi-Design Workspace
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HDL Debug and Analysis
Interactive Code Execution Tracing
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Advanced Breakpoint Management
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Signal Probes on Graphics/Animation of Graphics
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Memory Viewer
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FSM Debug
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Waveform Viewer (AWF and ASDB)
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Multiple Waveform Windows
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Waveform Stimulator
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Waveform Compare
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Waveform Editor
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Post Simulation Debug
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C++ Debugger
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Signal Agent (VHDL and Mixed Only)
Option
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X-Trace
Option
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Advanced Dataflow
Option
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Extra Standalone Accelerated Waveform Viewer (ASDB)
Option
Option
Simulation/Verification
Simulation Model Protection/Library Encryption
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VHDL/Verilog IEEE compatible Encryption
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Xilinx® Secure IP Support
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Value Change Dump (VCD and Extended VCD) Support
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Batch Mode Simulation/Regression (VSimSA)
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Profiler (Performance Metrics)
Option
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Verilog HDL Simulation Optimization
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VHDL Simulation Optimization
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Coverage Tools Bundle
Statement and Branch Coverage
Option
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Toggle Coverage
Option
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Expression and Condition Coverage
Option
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VHDL Path Coverage
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Lint - Design Rule Checking
Basic Lint (VHDL and Verilog)
Option
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ALINT™ (Advanced Lint)
Option
Option
Option
Option
External Simulation Interfaces
Synopsys SmartModels®, SWIFT™ Interface and LMTV
Option
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SpringSoft® Verdi™ PSD mode Interface
Option
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Co-simulation and C-Synthesis
Simulink® Co-simulation
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MATLAB® Co-simulation
Option
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Assertions Bundle
PSL IEEE 1850 Assertions and Coverage
Option
SystemVerilog IEEE 1800 Assertions and Coverage
Option
OpenVera Assertions and Coverage
Option
Documentation
Export to PDF/HTML/Bitmap Graphics
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Advanced Export to PDF (Vector Graphics)
Option
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Specialty Solutions
Zuken PCB Interface (CADSTAR and CR5000)
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Job Control Integration (Server Farm)
Option
Option
Licensing
Node Locked License
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Floating License
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One Year Time Based License
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Perpetual License
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Supported Platforms
Windows® 2000/2003/XP/Vista
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