EDA Tool vendors have been equipping their tools for ABV for the past five years, and if you’re in-the-market for an RTL Simulator, ABV should already be inside. No longer a methodology for "future designs" Assertion-Based Verification (ABV) is gaining momentum amongst designers. The 2005 introduction of IEEE SystemVerilog standard and its Assertions (subset), has since brought a key methodology into the mainstream language standard.
For today's designers, the question is not "will" you adopt assertions? Rather, "when" and "how" will you incorporate them into your designs? "In the past 4 years, SystemVerilog adoption has grown exponentially and one of the top design usages of this language has been assertions. Aldec has developed-in assertions support into its RTL simulators for over 5 years. Unlike our competition, Aldec continues to focus on the requirements from FPGA designers, now FPGA designers can affordably, adopt assertions and we've fully-integrated them throughout our RTL Simulators," said Lori Nguyen, Director of Marketing.

Aldec RTL Simulation Engines, Active-HDL™ and Riviera-PRO™ support ABV, and including SystemVerilog Assertions (SVA), Property Description Language (PSL), Functional Coverage Statements (Covers) and OVA/ Legacy Design support. Assertions are accessible throughout the entire design hierarchy, HDL source code, Waveform, debugging, code coverage and Aldec provides a dedicated Assertions viewer for visibility of Assertions throughout the design flow. Aldec Assertion Bundle Options (SVA, PSL and OVA) are available with Active-HDL and Riviera-PRO, call for details on how to add the bundle as an incremental option your existing license products.

Lori Nguyen, Director of Marketing – Aldec® Corporation

The name 'assertion' is one of the most misused words in EDA vocabulary. VHDL users think they already have them, Verilog® users think they don't really need them; all of them miss something important. This new methodology is based on design properties – those plain English descriptions encountered in every design specification. Traditionally, designers translate those properties into HDL descriptions that will be synthesized into real hardware. Property-Based Design (PBD) methodology suggests starting your work by writing down design properties in the formalized language that can be understood by most design and verification tools. Formalized design properties representing desired or unwanted design behaviors can be asserted, or their coverage can be checked in verification process. The beauty of this solution is that you can write properties, assertions and covers once, and they keep on reminding you what the original intent of your design is during the entire design and verification process. Learn more about Deploying Properties, Assertions and Covers download White Paper.

Assertions Are Coming To The Design Near You No matter if you are using VHDL, Verilog or mixture of pure HDLs in your designs, you will not be able to escape assertions. They are present in one form or another in all new verification techniques. You can start gently by trying out some library of property checkers, such as OVL, but investing some time in learning basics of PSL or SVA should be the important step in the career of every engineer.

Column written by Jerry Kaczynski, Technical Marketing Engineer, Aldec

Assertions - A Practical Introduction for HDL Designers The majority of FPGA designers who are proficient in traditional HDLs might have heard about assertions, but haven’t had time to try them out. Designers should be aware that assertions are quickly becoming standard part of both design and verification process, so learning how to use them is a future necessity. This webinar provides quick and easy introduction to the basic ideas and applications of assertions: sequences, properties, assert and cover commands, etc. Practical examples are used both during presentation and live demonstration in the simulator. View Webcast

Verilog® Coding Tricks and Techniques Knowing a few key tricks can help you avoid problems with simulation or synthesis, rather than debugging them later in the process. Soon the Verilog and SystemVerilog standards will merge, adding more features and increasing the possibility of coding mistakes. In this presentation, the most recent release on the language standard (Verilog-2005) and SystemVerilog Design Subset are discussed. View Webcast

Introduction to Xilinx® Secure IP Simulation of large, powerful FPGAs such as Virtex®-6 requires frequent use of Intellectual Property (IP). Distributing IP in the form of simulator-specific binaries is a management nightmare and more flexible C-based models are typically too slow. Thanks to newly added source-level encryption in major HDL standards, Xilinx® was able to create new system of fast and reliable IP delivery called Secure IP. This webinar presents theoretical and practical background of the Secure IP and highlights its usefulness by presenting new features of Virtex family and ISE 11.2 software. View Webcast