Aldec releases its latest RTL, gate and system-level simulator, Riviera-PRO 2010.06. The latest release supports OVM (Open Verification Methodology) and UVM (Universal Verification Methodology). Additionally, Riviera-PRO supports the most advanced verification, including ESL, TLM, and Assertion-based verification methodologies. The OVM aids engineers in developing reusable, interoperable verification IP and create hierarchical environments that facilitate “plug-and-play” reusable verification. Users of different expert levels can rely on OVM to quickly build up a layered, coverage driven, transaction-level verification environment that can be reused across different designs. Aldec Riviera-PRO 2010.06 provides a precompiled OVM library and SystemVerilog compatible simulator to help customers take advantage of this latest design verification technology to meet the challenge of verifying today’s complex designs. Riviera-PRO 2010.06 also supports assertion-based verification: assert statements, coverage statements, and properties.

Adam Sherer, Cadence Design Systems, Inc., Verification Product Management Director
"Cadence leads both OVM the UVM development to raise verification productivity throughout the industry. We welcome Aldec to the growing list of RTL simulation vendors in the ecosystem supporting the methodology common to both OVM and UVM and we look forward to further adoption by the entry and middle tier FPGA developers served by Aldec."

Aldec releases ALINT 2010.06 introducing Phase-Based Linting (PBL) – a new methodology that significantly improves user productivity and overall efficiency. The new methodology is available through structured and prioritized phases which minimize the number of design refinement iterations. Predefined and user defined templates are delivered with every rule library and offer a great starting point for creation of custom phases for quality control based on corporate standards. Download ALINT 2010.06 today, to evaluate the new Phase Based Linting methodology on your current design.

Always write your HDL code so that it can be easily reused. While RTL code naturally promotes reuse due to frequently occurring primitives, creating reusable testbench requires some discipline and initial additional work. VHDL and SystemVerilog packages help you to organize reusable code and popular methodologies such as OVM/UVM already contain reusable contents. Download White Paper – Meeting Growing Verification Demands

Column written by Jerry Kaczynski, Technical Marketing Engineer, Aldec

Using SystemVerilog for FPGA Design SystemVerilog includes a number of enhancements to the Verilog language that are useful for FPGA design and are supported by current FPGA synthesis tools. However, FPGA engineers may not have time in their schedules to learn the whole SystemVerilog language. In this webinar we explore how existing Verilog and VHDL users can start exploiting the synthesizable constructs of SystemVerilog when designing FPGAs. View Webcast

A Step-by-Step Guide to SystemVerilog Interfaces Modern digital designs have to transfer large amount of data across various blocks/IPs, especially in the SoC arena. SystemVerilog introduced a new construct called 'interface' that wraps data structures, transfer directions, protocol monitors in terms of assertions, cover properties and also compliance metrics via cover groups. This webinar explains typical elements of SystemVerilog interfaces and introduces basic concepts of using them in your designs and testbenches. View Webcast

VHDL 2008: Powerful, Easier to Use VHDL The latest version of the VHDL standard, IEEE Std 1076-2008 is the largest revision to date. It addresses virtually all annoyances of the old versions and adds exciting new features. Aldec has introduced support for many of these features in both their Active-HDL and Riviera products. Some synthesis vendors have introduced support in their tools. This webinar provides an in-depth overview of VHDL 2008 with a focus on either simplifying coding or making it more robust. View Webcast

Using FPGA Prototyping Board as an SoC Verification and Integration Platform Size of new designs has grown so much that it easily allows creation of the entire system containing microprocessor unit and peripherals on one chip. Verification of such designs can no longer rely on software only. The use of FPGA-based prototyping boards creates fast and economical solution to this problem. This paper presents one practical implementation of Prototyping Board Verification and Integration Platform. Download White Paper