VIP/IP Products

5G NR is the mobile broadband standard of the 5th generation. A new rate compatible structure for LDPC codes are employed for channel coding to fulfill the broad applications supported by the standard. Creonic’s 5G LDPC Decoder IP Core provides a perfect solution for this new LDPC structure with high level of flexibility while maintaining high throughput and low latency as required by the standard.

The Creonic AWGN Channel IP implements an AWGN noise generator capable of working up to a maximum of 512 symbols in parallel. The IP was developed with the aim of allowing the performance evaluation of a digital communication system in the presence of Additive White Noise and with a major emphasis on dealing with low bit-error-rates. Unlike a software-based AWGN generator, which might take several hours and even days for the stated purpose, a hardware-based AWGN generator requires significantly less time (reduces time by several orders of magnitude).

The Creonic CCSDS high performance modulator performs all tasks of an inner transmitter. The modulator expects SCCC (Serial Concatenated Convolutional Code) encoded frames as input and performs mapping, Physical Layer (PL) framing and modulation. In addition, the core performs baseband interpolation and output gain adjustment. The output of the core is designed to be followed by a DAC and RF front end.

The Creonic CCSDS 231.0 LDPC IP supports the LDPC coding schemes as defined by the CCSDS standard. The LDPC codes with rate 1/2, coded block lengths 128 and 512 are specially designed for telecommand applications, but the excellent error correction performance makes it the ideal fit for further applications with highest demands on forward error correction. The IP cores are available for ASIC and FPGAs (AMD Xilinx, Intel, Microchip).

The Creonic CCSDS AR4JA LDPC IP support the LDPC coding schemes as defined by the CCSDS standard. The LDPC codes with rates 1/2, 2/3 and 4/5, block lengths 1024, 4096 and 16384 are specially designed for deep-space missions, but the excellent error correction performance makes it the ideal fit for further applications with highest demands on forward error correction. The IP cores are available for ASIC and FPGAs (AMD Xilinx, Intel).

The Creonic CCSDS LDPC IP support the LDPC coding scheme as defined by the CCSDS standard. The LDPC code with single rate 223/255 was specially designed for Near-Earth missions, but the excellent error correction performance makes it the ideal fit for further high-throughput applications. The IP cores are available for ASIC and FPGAs (AMD Xilinx, Intel).

The recommended CCSDS 131.2-B-1 standard introduces a Serial Concatenated Convolutional Code (SCCC). Main goal of this code is to allow an efficient use of available bandwidth, by allowing to select from 27 valid configurations with a wide range of constellations, block lengths and code rates. The outstanding error correction performance of the SCCC code in combination with the high data rates makes this IP core the ideal fit for further applications where high throughput and high spectral efficiency is key for operation.

Data Over Cable Service Interface Specification (DOCSIS) is an international telecommunications standard that permits the addition of high-bandwidth data transfer to an existing cable TV (CATV) system. It is employed by many cable television operators to provide Internet access over their existing hybrid fiber-coaxial infrastructure. The Creonic LDPC Decoders covers all logical channels of DOCSIS 3.1:

• The Downstream (DS) Data Decoder decodes payload data with very high throughputs.
• The PLC (Physical layer Link Channel) Decoder decodes PLC frames and therefore allows conveying the physical properties of the OFDM channel.
• The Downstream (DS) NCP (Next Codeword Pointer) Decoder decodes NCP frames and therefore allows to convey plenty of information on the OFDM structure.

DVB-C2 (Digital Video Broadcast - Cable 2nd Generation) is an ETSI standard of the second generation for digital data transmission via cable networks. It complements the existing standards DVB-S2 and DVB-T2 for satellite and terrestrial communication and offers a capacity-approaching coding scheme. The Creonic DVB-C2 IP core integrates the forward error correction as defined by the standard (including LDPC and BCH decoder).

DVB-CID (Digital Video Broadcast - Carrier Identification System) is an ETSI standard for interference prevention within digital data transmission via satellites that was first published in 2013. Its goal is the identification of interfering transmissions from other sources, in order to respond to Radio Frequency Interference (RFI). The Creonic DVB-CID high performance modulator can be configured by a simple configuration interface and outputs a baseband signal split into real and imaginary part.

Creonic provides off-the-shelf IP cores for DVB-GSE encapsulation and decapsulation.

The DVB-GSE encapsulator performs the encapsulation of the network layer packets, also referred to as Protocol Data Units (PDUs), into one or more GSE packets, adding control information and performing integrity checks when necessary. Finally, it places the GSE packets into Baseband Frames (BBFRAMEs), ready for further processing by the Creonic DVB-S2X Modulators.

The Creonic DVB-GSE decapsulator performs the decapsulation of BBFRAMEs, containing one or more GSE packets. As a last step, it extracts the PDUs, i.e. the network layer packets, from the GSE packets.

DVB-RCS2 (Digital Video Broadcast - Second Generation DVB Interactive Satellite System) is the latest ETSI standard of the second generation for digital data transmission via satellites.

The Creonic DVB-RCS2 Multi-Carrier Receiver supports multiple frequency time domain multiple access (MF-TDMA), performs all tasks of an DVB-RCS2 receiver including carriers separation, baseband conversion, demodulation, and turbo decoding. It can process intermediate frequency (IF) real signal with center IF frequencies between 0 and 100 MHz. The Creonic turbo decoder is included in the receiver to provide users with Frame PDUs at the output.

Creonic provides IP cores for DVB-RCS2, in particular demapper, turbo decoder and this modulator. The Creonic DVB-RCS2 high performance modulator performs all tasks of a Modulator. The modulator expects PDU frames as input and performs energy dispersal, CRC encoding, turbo encoding, mapping, framing and modulation. In addition, the core performs baseband filtering and output gain adjustment. The output of the core is designed to be followed by a DAC.

DVB-RCS2 (Digital Video Broadcast - Second Generation DVB Interactive Satellite System) is the latest ETSI standard of the second generation for digital data transmission via satellites. It uses a new 16-state doublebinary turbo decoder that significantly outperforms its dated 8-state counterpart of DVB-RCS. DVB-RCS2 is the first standard to adopt these highest performance turbo codes. New modulation schemes (8-PSK and 16-QAM) help to increase spectral efficiency even further. The outstanding error correction performance of the DVB-RCS2 turbo decoder makes it the ideal candidate for further applications where high spectral efficiency is key for lowering costs.

DVB-RCS (Digital Video Broadcast - Interaction channel for satellite distribution systems) is an established ETSI standard for digital data transmission via satellites. It uses an 8-state double-binary turbo decoder that has an excellent error correction performance. This outstanding performance of the DVB-RCS turbo decoder makes it the ideal candidate for further applications where high spectral efficiency is key for lowering costs.

DVB-S2 (Digital Video Broadcast - Satellite 2nd Generation) is an ETSI standard of the second generation for digital data transmission via satellites. It was published in 2005, being the first standard of the second generation DVB standards (DVB-S2/-T2/-C2). Because of its capacity-approaching forward error correction, today DVB-S2 is the de-facto standard in satellite communication and other applications. The Creonic DVB-S2 IP core integrates the forward error correction as defined by the standard (including LDPC and BCH decoder).

Creonic provides IP cores for DVB-S2X demodulation, LDPC/BCH decoding as well as modulation. The Creonic DVB-S2X high performance modulator performs all tasks of an inner transmitter. The modulator expects BBFrames after mode adaptation as input and performs stream adaptation, FEC encoding, mapping, PL framing and modulation. In addition, the core can perform baseband interpolation and output gain adjustment. The output of the core is designed to be followed by a DAC and RF front end.

Creonic provides the following field-proven IP cores:

• DVB-S2X Modulator M100 / M400
• DVB-S2X Demodulator
• DVB-S2X LDPC/BCH Decoder

DVB-S2X Modulator M100 / M400

The Creonic DVB-S2X high performance modulator performs all tasks of an inner transmitter. The modulator expects BBFrames after mode adaptation as input and performs stream adaptation, FEC encoding, mapping, PL framing and modulation. In addition, the core can perform baseband interpolation and output gain adjustment. The output of the core is designed to be followed by a DAC and RF front end.

Creonic provides IP cores for wideband (500 Msymb/s) DVB-S2X demodulation, LDPC/BCH decoding as well as modulation. The Creonic DVB-S2X high performance wideband modulator performs all tasks of an inner transmitter. The modulator expects BBFrames after mode adaptation as input and performs stream adaptation, FEC encoding, mapping, PL framing and modulation. In addition, the core can perform baseband interpolation and output gain adjustment. The output of the core is designed to be followed by a DAC and RF front end.

GEO-Mobile Radio (GMR) is an ETSI standard for satellite phones. The Creonic GMR Decoder IP core supports the PNB2 burst packets that were added in GMR Release 2 (GMPRS-1) and use LDPC codes for the first time. The same burst modes and LDPC codes are also in GMR Release 3 (GMR-3G). The Creonic GMR LDPC decoder IP core is a field-proven solution.

The WiGig standard (IEEE 802.11ad) delivers data rates of up to 7 Gbit/s and hence outperforms the current IEEE 802.11n standard by more than 10x. It uses the 60 GHz band to enable short range communication and interoperability between a broad set of applications and platforms. The Creonic WiGig LDPC decoder is designed in particular to deliver highest throughputs in the multi-gigabit domain with a small footprint. At the same time it provides outstanding error correction performance, resulting in a low energy consumption and increasing range of wireless transmission. Its unique pipeline architecture can be customized at design-time to deliver best performance on any target technology. Insertion, removal and balancing of pipeline stages within the IP core is flexible and allows for optimization of required routing resources, path delays between pipeline stages, throughput, and footprint at the same time.

The WiFi family of standards (IEEE 802.11) is used for Wireless Local Area Networks (WLANs). Its first version from 1997 has been extended by many amendments such as IEEE 802.11n-2009 (now part of IEEE 802.11- 2012). This amendment was developed in particular for high throughputs of 600 Mbit/s on the air interface. The standard uses convolutional codes for forward error correction as minimum requirement. LDPC codes are optional but because of their superiority over convolutional codes they are widely used today. The Creonic IEEE 802.11 LDPC decoder is a high performance implementation for WLAN and further applications and supports all LDPC codes as defined by the standard.

The WiFi family of standards (IEEE 802.11) is used for Wireless Local Area Networks (WLANs). Its first version from 1997 has been extended by many amandments such as IEEE 802.11n-2009 (now part of IEEE 802.11-2012). This amendment was developed in particular for high throughputs of 600 Mbit/s on the air interface. The standard uses convolutional codes for forward error correction as minimum requirement. LDPC codes are optional but because of their superiority over convolutional codes they are widely used today.

The Creonic IEEE 802.11 LDPC decoder is a high performance implementation for WLAN and further applications and supports all LDPC codes as defined by the standard.

The IEEE 802.15 working group specifies standards targeting the wireless personal area network (WPAN). Task group 3 of the working group focuses on high data rates within WPAN. The task group 3c defined a new millimeter-wave-based alternative physical layer (PHY) for the IEEE 802.15.3-2003 standard. This standard (IEEE 802.15.3c-2009) operates at 60 GHz and offers data rates of multiple Gbit/s for applications such as high speed internet access or streaming content download. The task group adopted LDPC codes for these high data rate modes within the single carrier (SC) mode and the high speed interface (HSI) mode.

The Creonic IEEE 802.15.3c LDPC Decoder IP supports all LDPC codes with a codeword size of 672 bits as defined by the standard.

• Compliant with IEEE 802.3bj, Clause 91
• Support for KR4 (528, 514) and KP4 (544, 514) Reed-Solomon (RS) code
• Corrects up to seven (KR4) or up to 15 (KP4) erroneous symbols.
• High-throughput, low-latency core.
• Support for single channel mode (up to 100 Gbit/s).
• Support for bypass mode with low latency.
• Symbol error measurement per lane.
• Detection of un-correctable code words.
• Block-to-block on-the-fly switching between KP4/KR4 codes.
• Easy-to-use handshaking interfaces.
• No internal RAM required.
• Available for ASIC and FPGAs (AMD Xilinx, Intel).
• Deliverable includes Verilog source code or synthesized netlist, VHDL testbench, and bit-accurate Matlab, C or C++ simulation model.

The ITU-T G.9804.2 Recommendation defines the common transmission convergence (ComTC) layer used in Higher Speed Passive Optical Networks.

The Creonic ITU 25G PON LDPC Encoder and Decoder are part of the Forward Error Correction (FEC) of the ComTC layer. These components are designed to support both the default LDPC(17280, 14592) coding scheme and the optional LDPC(17152, 14592) scheme, providing flexibility and adaptability to meet the specific needs of different network configurations.

The IP cores are available for ASIC and FPGAs (AMD Xilinx, Intel, Microchip).

Creonic’s LTE/LTE-A IP Core is an advanced, customer-proven implementation of the standardized 3GPP turbo code. The turbo decoder was designed for base station and user equipment applications. However, the high flexibility in block lengths and code rates makes it the ideal fir for further applications.

MIMO (Multiple Input Multiple Output) techniques are being used more and more in recent and upcoming standards since they drastically outperform traditional SISO (Single Input Single Output) techniques in terms of maximum throughput and range. This gain results from an increased spectral efficiency, lowering the overall system costs.

A Minimum Mean Square Error (MMSE) MIMO detector is an integral part of a MIMO receiver. The Creonic MMSE detector offers high throughputs even on low-cost FPGAs and convinces with a low implementation complexity at the same time. Its flexibility at design-time and run-time makes it the ideal fit for all kinds of MIMO applications.

Polar codes are a trending family of forward error correction codes currently gaining a place in the realm of digital communications, which exhibit a particularly high performance while requiring a low-complexity implementation. They were first adopted by the 3GPP 5G NR standard.

Rate-Flexible Polar Encoder
The Creonic Polar Encoder IP core is a scalable solution featuring code-rate flexibility, high throughput and very low latency on state-of-the-art FPGAs. Since a polar encoder normally requires information data to be presented in a certain way at its input, the Creonic Polar Encoder IP takes care of this in a pre-encoding stage. This important feature, with aid of AXI4-Stream interface ports, allows a very straight-forward integration of the core into any system.

The Optical Communications Terminal (OCT) Standard was developed by the Space Development Agency (SDA) with the purpose of bringing interoperability across freespace optical communication (FSO) systems where at least one endpoint is a space-based terminal.

The Creonic SDA OCT V3.0 Encoder is designed to generate Over-The-Air (OTA) frames in accordance with the OCT standard. These frames consist of a preamble, followed by a header and payload data, both of which are protected with cyclic redundancy check (CRC) and forward error correction (FEC) for better data integrity.

The Creonic SDA OCT V3.0 Decoder performs the synchronization of the Over-The-Air (OTA) frame and then decodes the header and payload data within the frame.

BCH codes are widely used where bit errors are scattered randomly within the codeword. The Creonic Ultrafast BCH Decoder is capable of processing an entire BCH codeword per clock cycle in a pipelined way. Therefore, tt achieves outstanding data rates.

The design can be parameterized at design-time to support different codeword sizes and code rates. Latency can be adjusted by insertion or removal of pipeline register stages.

Convolutional codes are widely adopted in wireless communication systems for forward error correction. Creonic offers you an open source Viterbi decoder with AXI4-Stream interface, that is capable of decoding most of the convolutional codes as defined by various standards.

The Creonic Wideband Digital Down Converter (DDC) digitally converts the input signal at IF frequency down to baseband by multiplying input samples with sine/cosine waves generated by numerical controlled oscillators (NCO). Down converted samples are then decimated by
a factor ranging from 2 to 512 with multiplying step of 2. A CIC and 4 stages of half band filters are integrated within the decimator.

The core accepts a real signal at input and provides complex I/Q baseband data at the output. The parallel architecture of the core allows for an input throughput up to 2.4 Gsps, data symbol rate up to 540 Msymb/s, making it a perfect fit for ultra high throughput applications such as wideband DVB-S2X communication.

The solution from Creonic for data rates of up to 1 Gbit/s offers outstanding efficiency in terms of implementation complexity. Area and energy efficiency played a decisive role during the LDPC code design process. With this unified approach not only outstanding efficiency is
obtained, but also excellent error correction performance, outperforming Viterbi decoders by up to 3 dB. At the same time, a throughput of hundreds of Mbit/s can be achieved even on low-cost FPGAs.

Serial Front Panel Data Port is an industry standard, low-overhead, low-latency, high speed serial communications protocol. sFPDP is ideal for use in applications such as high-speed communication system backplanes, high-bandwidth remote sensor systems, signal processing, data recording, and high-bandwidth video systems. The simple and lightweight nature of the protocol makes it an attractive choice for replacement of parallel bus interconnects using serial transceiver technology. sFPDP can be used in point-topoint or loop topologies, uni-directional or bidirectional links, and easily supports different types of data with efficient and flexible data framing options.

The Northwest Logic AXI DMA Back-End Core provides high-performance, scatter-gather DMA operation in a flexible fashion. This enables the core to be easily integrated and used in a wide variety of DMA-based systems.

The CSI-2 Controller Core V2 is Northwest Logic’s second generation CSI-2 controller core. It is further optimized for high performance, low power and small size.

The Northwest Logic DMA Back-End Core provides high-performance, scatter-gather DMA operation in a flexible fashion. This enables the core to be easily integrated and used in a wide variety of DMA-based systems.

The DSI-2 Controller Core is Northwest Logic’s second generation DSI controller core. It is further optimized for high performance, low power and small size.

The DSI Controller Core is part of Northwest Logic’s MIPI Solution. This solution is designed to achieve maximum MIPI throughput while being easy to use.

The Expresso 3.0 Core is part of Northwest Logic’s PCI Express Solution. This solution is designed to achieve maximum PCI Express throughput while being easy to use.

The Expresso 4.0 Core is part of Northwest Logic’s PCI Express Solution. This solution is designed to achieve maximum PCI Express throughput while being easy to use.

The Northwest Logic Expresso DMA Bridge Core provides high-performance DMA and/or bridging between PCI Express and AXI for both Endpoint and Root Port applications.

The Northwest Logic Expresso DMA Core provides high-performance, scatter-gather DMA operation in a flexible fashion. This enables the core to be easily integrated and used in a wide variety of DMA-based systems.

Highly capable loss-less data compression and expansion cores capable of >1Gbps throughputs in FPGA without any requirement for external RAM.

Easy to use and highly integrated AES-CCM cores offering combined encryption and data authentication in a single engine.  Compliant with standards like 802.11, 802.15, 802.16, Zigbee, IEEE1619.1.

Easy to use and highly integrated AES-GCM cores offering combined encryption and data authentication in a single engine.  Compliant with standards like IPsec,

Easy to use and highly integrated AES Key Unwrap core, implementing the NIST AES Key Unwrap algorithm and AESKW mode of ANS X9.102.

Easy to use and highly integrated AES Key Wrap core, implementing the NIST AES Key Wrap algorithm and AESKW mode of ANS X9.102.

Cryptographic Pseudo Random Number Generator which implements ANSI X9.17 and X9.31 PRNGs based on either Triple-DES or AES encryption algorithms.

Easy to use block cipher core which implements DES and Triple-DES encryption and decryption to NIST FIPS publication 46-3.

Easy to use CSA core implements ETSI specified DVB Common Scrambling Algorithm which is ideal for use in BISS-E and BISS Mode-1 Digital Satellite News Gathering applications.

Low latency, high data rate AES (Advanced Encryption Standard) encryption and decryption IP cores supporting 128, 192 and 256-bit key sizes.

Easy to use Fast Hashing cores supporting the MD5, SHA-1, SHA-256, SHA-384 and SHA-512 hashing algorithms, aimed at high data rate applications.

Easy to use core which implements the Z = Y^E mod M, the Modular Exponentiation function commonly used in Public-Key Cryptography and ideal for hardware acceleration of RSA, Diffie-Hellman and DSA.

Super compact multi-mode Hashing core supporting the MD5, SHA-1, SHA-224, SHA-256, SHA-384 and SHA-512 hashing algorithms, each with optional HMAC, aimed at low rate applications.

Compact, mid data rate AES (Advanced Encryption Standard) encryption and decryption IP cores supporting 128, 192 and 256-bit key sizes.

Ultra low area, low data rate AES (Advanced Encryption Standard) encryption and decryption IP cores supporting 128, 192 and 256-bit key sizes.

Aldec 1-Wire Slave transactor provides capability to communicate over 1-Wire bus. It consist of fully synthesizable hardware part written in Verilog and software part written in C and SystemVerilog with API in SystemVerilog. Hardware and software parts communicate through the Standard Co-Emulation Modelling Interface (SCE-MI)

Aldec AMBA High-performance Bus (AHB) transactor provides communication and monitoring capabilities with AHB devices (master and slave). It consist of fully synthesizable hardware part written in SystemVerilog and testbench part written in C++ with SystemVerilog API. Hardware and testbench parts communicate through the Standard Co-Emulation Modelling Interface (SCE-MI) using function based message passing (DPI)

Aldec AMBA High-performance Bus (AHB) transactor provides communication and monitoring capabilities with AHB devices (master and slave). It consist of fully synthesizable hardware part written in VHDL and software part written in C++ with API in C. Hardware and software parts communicate through the Standard Co-Emulation Modeling Interface (SCE-MI) using macro based message passing use model

Aldec AMBA Advanced eXtensible Interface (AXI) transactor provides communication and monitoring capabilities with AXI devices (master and slave). It consist of fully synthesizable hardware part written in SystemVerilog and testbench part written in C++ with SystemVerilog API. Hardware and testbench parts communicate through the Standard Co-Emulation Modelling Interface (SCE-MI) using function based message passing (DPI)

CSIX-L1 is a Common Switch Interface, for transferring information between switching fabric and traffic
managers (network processors).
The Aldec CSIX transactor provides capability to communicate over CSIX networking interface.
It consists of:
- fully synthesizable hardware part written in Verilog
- software part written in C and SystemVerilog
- Low Level API in SystemVerilog (giving full control, e.g. of flow control)
- High Level API in SytemVerilog (taking care of flow control)
Hardware and software parts communicate through the Standard Co-Emulation Modelling Interface (SCE-MI)

The Aldec Ethernet transactor provides capability to communicate over Ethernet networking interfaces:
- 1000 Mb/s (Gigabit Ethernet)
- 100 Mb/s (Fast Ethernet)
- 10 Mb/s
It consists of:
- fully synthesizable hardware part written in Verilog
- software part written in C and SystemVerilog
- API in SystemVerilog
Hardware and software parts communicate through the Standard Co-Emulation Modelling Interface (SCE-MI)

The Aldec Ethernet speed adapter provides capability to connect real-speed (up to 1000 Mbit/s) Ethernet interface to Ethernet DUT in Aldec emulator. Speed adapter handles synchronization between two domains (fast/real and slow/emulator) and manages protocol-specific flow control.

Aldec Inter-Integrated circuit (I 2C)  transactor provides capability to communicate over I 2C bus. It consist of fully synthesizable hardware part written in VHDL and software part written in C++ with API in C. Hardware and software parts communicate through the Standard Co-Emulation Modelling Interface (SCE-MI) using macro based message passing use model

Aldec Inter-IC Sound (I2S) transactor provides capability to communicate over I2S bus. The I2S transactor uses one channel but combines both transmitter and receiver functions. Communication between an HDL model with a C model is provided by Standard Co-Emulation Modelling Interface (SCE-MI)

Aldec IEEE 1 149.1 Standard Test Access Port and Boundary-Scan Architecture (Joint Test Action Group JTAG )  transactor provides capability to communicate over JTAG interface. It consist of fully synthesizable hardware part written in VHDL and software part written in C++ with API in C. Hardware and software parts communicate through the Standard Co-Emulation Modelling Interface (SCE-MI) using macro based message passing use model

Aldec Tensilica JTAG transactor provides capability to connect software debugger (e.g. gdb or eclipse-based) to Tensilica CPU, without physical JTAG cable. It consist of fully synthesizable hardware part written in SystemVerilog and software library for Tensilica XOCD. Hardware and software parts communicate through the Standard Co-Emulation Modelling Interface (SCE-MI) using function based message passing (DPI)

Aldec OCP (Open Core Protocol) version 2.1 provides capability to communicate over OCP bus as master and slave. It consists of fully synthesizable hardware part written in VHDL and software part written in C++ with API in C. Communication between HDL and C model is provided by Standard-CoEmulation Modelling Interface (SCE-MI)

Aldec PCI Express transactor provides communication capabilities with PCIe devices. It consist of fully synthesizable hardware part written in SystemVerilog and testbench part written in C++ with SystemVerilog API. Hardware and testbench parts communicate through the Standard Co-Emulation Modelling Interface (SCE-MI) using function based message passing (DPI).

The Aldec PCI Express speed adapter provides capability to connect real-speed PCIE device to PCIe DUT in Aldec emulator. Speed adapter handles synchronization between two domains (fast/real and slow/emulator) and manages protocol-specific flow control.

ALDEC SPI 4.2 transactor provides communication with Link Layers devices with SPI 4.2 interface. It consist of fully synthesizable hardware part written in SystemVerilog and testbench part written in C++ with SystemVerilog API. Hardware and testbench parts communicate through the Standard CoEmulation Modelling Interface (SCE-MI) using function based message passing (DPI)

Aldec TLM2SCEMI_AHB gives ability to connect Virtual Platform with AMBA AHB-based SoC in emulator. Hardware and software parts communicate through the Standard Co-Emulation Modelling Interface (SCE-MI) using macro based message passing use model

Aldec TLM2SCEMI_AXI gives ability to connect Virtual Platform with AMBA AXI-based SoC in emulator. Hardware and software parts communicate through the Standard Co-Emulation Modelling Interface (SCE-MI) using macro based message passing use model

Aldec UART transactor provides capability for serial communication with devices like CPU. It consists of fully synthesizable hardware part written in VHDL and software part written in C++ with API in C. Communication between HDL and C model is provided by Standard Co-Emulation Modelling Interface (SCE-MI)

Aldec Universal Serial Bus device transactor provides capability to communicate over USB2.0 bus. It consist of fully synthesizable hardware part written in SystemVerilog and software part written in C++ with C API. Hardware and software parts communicate through the Standard Co-Emulation Modelling Interface (SCE-MI) using macro based message passing

The Aldec USB speed adapter provides capability to connect real-speed USB device to USB DUT in Aldec emulator. Speed adapter handles synchronization between two domains (fast/real and slow/emulator) and manages protocol-specific flow control.

Aldec WISHBONE Master Transactor provides capability to communicate over WISHBONE bus in Classic Mode. It consists of fully synthesizable hardware part written in VHDL and software part written in C++ with API in C. Communication between HDL and C model is provided by Standard Co-Emulation Modelling Interface (SCE-MI)