Active-HDL Designer Edition provides FPGA designers with an RTL simulator for less than $2,000 and includes: industry proven IEEE mixed-language simulation support for VHDL, Verilog® and SystemVerilog (Design), with 2X-plus performance gains over FPGA supplied RTL simulators, encrypted IP support and no limitations on FPGA device size.
Active-HDL Designer Edition
- Mixed-language simulator
- VHDL IEEE 1076 (1987, 1993, 2002 and 2008)
- Verilog® HDL IEEE 1364 (1995, 2001 and 2005)
- SystemVerilog IEEE 1800 (Design)
- Performance 2X+ faster performance then FPGA vendor simulators on average
- Debugging Waveform viewer, memory viewer and code execution tracing
- Encrypted IP IEEE VHDL and Verilog IP support
- Unlimited Device Size support
- HDL design tools Mixed-language design entry, state machine, block diagram and HDL editor
- Design Flow Manager Integrates third-party tools (synthesis and place/route- 85 sub applications).
- Windows® 32/XP/Vista
- One year time based license