Play WebinarTitle: Making a Structured VHDL Testbench – A Demo for BeginnersDescription: Wait for flag or interrupt or a given value – with a timeout Check that signals have been stable – without pulses or spikes for a given time Report an alert summary … and more …all using well-documented VHDL procedures and functions from UVVM, the open source fastest growing VHDL verification methodology. The presented solution will use UVVM Utility Library and BFMs, but the principles and mechanisms are 100% general verification methodology; i.e., independent of library and available functionality. Although this testbench is applied on a very simple design under test (DUT), the same principles also apply to advanced testbenches for complex DUTs. (But the advanced testbenches need more on top.) Agenda: > Quality and Efficiency Enablers > The simple DUT and simple TB architecture > UVVM: Concepts, Download and Compile > Making the testbench – prior to test cases > Adding clock generator and starting logging and checking > BFMs: Explained, Usage, Making simple overloads > Alert handling, Verbosity control and Timeouts > Conclusion > Q&ASigning up for an account is easy. With an Aldec account you'll have easy, one-click access to event registration, support, product downloads, evaluation licenses, recorded webinars, white papers, application notes and other resources. Simply provide your corporate e-mail address below - all account requests are verified and confirmed within 48 hours. If you already have an Aldec account, please Sign In below to download the file. Register Sign In
