Title: OS-VVM: High-Level VHDL Verification
Description: When facing the challenging task of implementing Constrained Random Stimulus or Functional Coverage in their testbench, VHDL designers used to make difficult choice between "reinventing the wheel" (writing appropriate code from scratch) and "using a square wheel" (using SystemVerilog for verification). Fortunately, there is now a third option available: Open Source VHDL Verification Methodology. OS-VVM is a set of VHDL packages that provide reliable, field-tested procedures and functions handling randomization and functional coverage. This webinar will demonstrate the structure and use of OS-VVM packages, paying special attention to Smart Coverage that combines random stimulus and functional coverage to provide faster verification.
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