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Aldec unwraps SoC/ASIC verification platform at ‘Verification Futures 2012’ in Europe

Date: Dec 3, 2012Type: Release

Basingstoke, United Kingdom - December 3, 2012 - Aldec, Inc. joined other top-tier EDA solution providers at the successful Verification Futures conference held in the United Kingdom. Aldec’s recently launched HES-7™ ASIC prototyping solution coupled with its HES-DVMTM emulation platform was well-received by conference attendees for its ability to accommodate up to 96 million ASIC gates and provide SoC software engineers with an early hardware platform to facilitate efficient software/hardware co-design and co-verification.

 

Known as ‘The Design Verification Company’, Aldec was on hand to share solutions to the top EDA challenges identified by the user community. During the conference, Aldec Hardware Division Sr. Application Engineer, Jacek Majkowski, further detailed hot-topic solutions with a paper on Platform Validation. Mr. Majkowski shared customer case studies citing successful deployment of Aldec’s HES-DVM emulation platform using SCE-MI 2.0 transactor co-verification methodologies for early validation of next-generation SoC designs.

 

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Dr. Mike Bartley, founder and CEO of event organizer Test and Verification Solutions (TVS), commented: “The increasing importance of verification methodologies, and the need for more ‘intelligent’ verification cycles, was highlighted by a number of vendors and delegates. It was particularly useful to have Aldec here to explain how their products meet these challenges. Users also liked the ability of Aldec’s technology to take them from simulation to emulation using a common testbench.”

 

Dave Rinehart, Aldec Vice President, added: “We would like to congratulate TVS on the great success of Verification Futures which included participants from 200 companies in 27 countries. As Aldec is a customer-focused organization, receiving direct feedback in an open peer-to-peer forum was valuable and will contribute to our future development plans as we strive to meet our customers’ growing verification requirements.” 

 

About Verification Futures

Verification Futures, organized by Test and Verification Solutions (TVS), is a free conference and networking event for verification engineers to discuss industry challenges, recently held in the European cites of Windsor/United Kingdom, Grenoble/France and Munich/Germany. All the presentations are available on the TVS website: www.testandverification.com.  In 2013, Verification Futures will also be held in the U.S. and India.

 

About Aldec

Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, ASIC Prototyping, Design Rule Checking, IP Cores, DO-254 Functional Verification and Military/Aerospace solutions. www.aldec.com  


Aldec is a registered trademark of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners.

Media Contact: Christina Toole,
Aldec, Inc.
+1.702.990.4400
christinat@aldec.com
www.aldec.com