90’s Kid Active-HDL Celebrates Sweet 16
Serving FPGA Designers as the tool of choice since, like, forever
As the proud Product Manager of Aldec’s FPGA Design Simulation solution, I am excited (like it was my first Cranberries concert) to announce that Active-HDL™ is celebrating 16 years since its initial release in 1997. Active-HDL has not merely stood the test of time, it has dominated the FPGA market like a Hulk Hogan smackdown with powerful simulation performance and debugging tools.
The key to Active-HDL’s long-term success lies in Aldec’s customer-centric philosophy. Simply put, we really do listen closely to our users and invest heavily in our tools. For this reason, continued simulation performance optimizations from release to release enable users to benefit from Active-HDL’s faster simulation even as the size of FPGA designs continues to grow.
Active-HDL has even recently won the Top FPGA Design, Verification and Simulation Platform for the fourth consecutive year by Chinese Electronics News (CEN). Here’s an excerpt from today’s press release:
Active-HDL, Aldec’s all-in-one tightly integrated solution offering design creation, documentation, code coverage and simulation, was awarded the 2013 Excellence Award - FPGA Tools for the fourth consecutive year by Chinese Electronics News (CEN). This prestigious award, recognizing top contributors in the semiconductor industry, was presented at China’s fifth annual FPGA Industry Development Forum.
“Active-HDL has evolved tremendously since its initial launch in 1997 and continues to be the tool of choice for FPGA designers,” said Satyam Jani, Aldec Software Division Product Manager, “Aldec’s receipt of this prestigious award demonstrates our commitment to investing in our products to continually meet the growing needs of the FPGA design community.”
You can view the rest of this press release in the Aldec Newsroom.
For more on Active-HDL including resources and free evaluation download, visit www.aldec.com/products/active-hdl or check out these resources:
White Paper: Corporate Standardization of FPGA Design Flow
Recorded Webinar (Part 1 of 3): Fast Track to Active-HDL