Products Overview

Active-HDL™ is a Windows® based integrated FPGA Design Creation and Simulation solution. Active-HDL includes a full HDL graphical design tool suite and RTL/gate-level mixed-language simulator.

Riviera-PRO™ verification platform delivers advanced design entry, simulation, debugging, and verification tools based on cutting edge technology.

ALINT™ design analysis tool decreases verification time dramatically by identifying critical issues early in the design stage. Smart design rule checking (linting) points out coding style, functional, and structural problems that are extremely difficult to debug in simulators and prevents those issues from spreading into the downstream stages of design flow.

DVM™ is the main software of HES facilitating easy design setup and flexibility with its fully scriptable environment, ASIC to FPGA clock conversion, automatic design partitioning, advanced HDL compiler, incremental compilation and interface with commercial simulators.

Aldec and Microsemi have joined together, offering a new, innovative, reprogrammable prototyping solution for Microsemi RTAX-S/SL, RTAX-DSP and RTSX-SU space-fight system designs. Unlike the traditional OTP (One Time Programmable) anti-fuse space-qualified FPGAs, the Aldec prototype adaptor uses flash-based, Microsemi ProASIC®3E FPGA technology, for design prototype re-programmability.

The DO-254/CTS™ provides a guide to the development of designs for complex electronic hardware in avionics. Complex electronic hardware includes devices such as FPGAs, PLDs, and ASICs.