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FPGA and ASIC Verification Products

	Design Creation	Verification	Specialty Solutions
FPGA Verification
Active-HDL 8.2	Schematic / Block Diagram Editor Code2Graphics State Machine Editor FPGA Project Management IP Core Generator Testbench Generation Documentation (HTML/PDF)	VHDL Simulation Verilog Simulation SystemC SystemVerilog Coverage Tools Design Rule Checker	MATLAB/Simulink Co-Simulation Verification IP HDL Regression Manager	Download Configurations Brochure (.pdf) Read More
ASIC/FPGA Verification
ALINT 2010.06	Basic HDL Text Editor	Phase-Based Linting (PBL) FPGA Primitive Support Design Rule Checker	DO-254 HDL Design Rules	Download Configurations Brochure (.pdf) Read More
Riviera-PRO 2010.06	HDL Text Editor	VHDL Simulation OVM and UVM Support Verilog Simulation SystemC SystemVerilog Assertions (PSL, SVA and OVA) Verilog Simulation Optimization VHDL Simulation Optimization Coverage Tools Design Rule Checker	MATLAB/Simulink Co-Simulation Verification IP HDL Regression Manager	Download Configurations Brochure (.pdf) Read More
In-Hardware Verification
HES 2010.02		Acceleration/Emulation Prototyping	NIOS II Co-Verification ARM Co-Verification	Download Configurations Brochure (.pdf) Read More
Specialty Solutions
Actel RTAX and RTSX Prototyping			Actel RTAX/RTSX Prototyping Actel RTSX Prototyping EDIF Netlist Conversion	White Paper Brochure (.pdf) Read More
DO-254 CTS			Code Coverage DO-254 Tool Assessment and Qualification DO-254 In-Hardware Simulation DO-254 HDL Design Rules	Download Brochure (.pdf) Read More
IP Products
IP Products	IP Core Generator		Verification IP	Read More