FPGA and ASIC Verification Products

 
Design Creation Verification Specialty Solutions
FPGA Verification

Active-HDL 8.2

Schematic / Block Diagram Editor
Code2Graphics
State Machine Editor
FPGA Project Management
IP Core Generator
Testbench Generation
Documentation (HTML/PDF)
VHDL Simulation
Verilog Simulation
SystemC
SystemVerilog
Coverage Tools
Design Rule Checker
MATLAB/Simulink Co-Simulation
Verification IP
HDL Regression Manager
ASIC/FPGA Verification

ALINT 2010.06

Basic HDL Text Editor
Phase-Based Linting (PBL)
FPGA Primitive Support
Design Rule Checker
DO-254 HDL Design Rules

Riviera-PRO 2010.06

HDL Text Editor
VHDL Simulation
OVM and UVM Support
Verilog Simulation
SystemC
SystemVerilog
Assertions (PSL, SVA and OVA)
Verilog Simulation Optimization
VHDL Simulation Optimization
Coverage Tools
Design Rule Checker
MATLAB/Simulink Co-Simulation
Verification IP
HDL Regression Manager
In-Hardware Verification

HES 2010.02

Acceleration/Emulation
Prototyping
NIOS II Co-Verification
ARM Co-Verification
Specialty Solutions

Actel RTAX and RTSX Prototyping

Actel RTAX/RTSX Prototyping
Actel RTSX Prototyping
EDIF Netlist Conversion

DO-254 CTS

Code Coverage DO-254 Tool Assessment and Qualification
DO-254 In-Hardware Simulation
DO-254 HDL Design Rules
IP Products

IP Products

IP Core Generator
Verification IP