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Build Information

Platform:All Platforms
Release Date:9/25/2008
Build:EURO AVMS I-03 - Beyond Vendor Supplied Verification Tools
Build Type:Series I (EU)

Instructions

Date of presentation: Thursday 9/25/2008, 3:00 PM (Central European Summer Time (CEST))

Presenter: Aldec, Inc. Jaroslaw Kaczynski, Technical Marketing Engineer

Abstract: Vendor-supplied FPGA development tools are inexpensive (sometimes free) and in some areas (e.g. implementation or place & route) indispensable. When you have to deal with advanced methods of design entry and management or perform lengthy simulation of large circuits, they provide only basic functionality. If you have to work with more than one FPGA vendor, using their tools also means switching between totally different environments when you switch vendors. You can get better results faster (and in more comfortable environment) by using independent design entry, management and simulation tools.

Agenda:

· Vendor independent design management

· Advanced text and graphical design entry

· High-performance simulation

· State-of-the-art debugging tools

· Automated design documentation

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What FPGAs interest you?:	Actel Altera Lattice Quicklogic Xilinx
Which HDL's interest you?:	Assertions OVL/PSL/SVA SystemC/C/C++ SystemVerilog Verilog VHDL
Are you interested in any specialty solutions:	Actel RTAX prototyping ASIC design rule checking (LINT) ASIC emulation/prototyping DO-254 compliance Matlab/Simulink co-simulation
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