Aldec - Webinars - Download

Build Information

Platform:All Platforms
Release Date:12/3/2009
Build:Europe - VHDL Coding Tips and Techniques
Build Type:HDL Languages

Instructions

Date: Thursday, December 3, 2009
Time: 3:00 pm – 4:00 pm CET
Location: On-Line

Abstract:
VHDL has added many new features since the publication of the first standard 22 years ago, but continues to benefit from the robustness and clarity of the original language definition. Based on experience gained from training many thousands of engineers, this webinar will help to reinforce your understanding of some of the key VHDL concepts that can make the difference between being a novice user and an expert. We will also focus on some common pitfalls and their solutions, thus helping you to make better, more efficient use of the language.

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What FPGAs interest you?:	Actel Altera Lattice Quicklogic Xilinx
Which HDL's interest you?:	Assertions OVL/PSL/SVA SystemC/C/C++ SystemVerilog Verilog VHDL
Are you interested in any specialty solutions:	Actel RTAX prototyping ASIC design rule checking (LINT) ASIC emulation/prototyping DO-254 compliance Matlab/Simulink co-simulation
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