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Active-HDL EDU Configuration

 

Features
EDU Editions
Active-HDL
EDU Edition
Active-HDL
Student Edition
Project Management
Support for Multi-Design Workspace
Single Design
Design Flow Manager For FPGA Vendors
Design Entry
HDL, Text, Block Diagram and State Machine Editor
30 fubs/states
Code Generation Tools
Testbench Generation from Waveforms
IP Core Component Generator
Code Generation Tools
Standard Waveform Editor and List Viewer (AWF)
Co-Simulation
Simulink® Co-Simulation
MATLAB® Co-Simulation
 
Documentation
Export to PDF/HTML/Bitmap Graphics
 
30 fubs/20 states
Simulation
VHDL IEEE 1987, 1993, 2002 and 200x
Ref. Note (1) and (2)
Ref. Note (1) and (2)
Verilog® HDL IEEE 1995, 2001 and 2005
Ref. Note (1) and (2)
Ref. Note (1) and (2)
SystemC™ 2.2 IEEE 1666/OSCI 2.2
 
Ref. Note (1) and (2)
SystemVerilog IEEE 1800 (Design)
Ref. Note (1) and (2)
 
EDIF 2.0.0
Ref. Note (1) and (2)
 
Mixed Language
Verilog Programming Language Interface (PLI/VPI)
 
Licensing
Node Locked License
Free Time-Based,
Licensed to software ID
Floating License
 
 
Notes:
(1) Simulation performance limitations compared to full commercial release of Active-HDL.
Performance Restrictions
Slow down
Active-HDL EDU Edition
4x
Active-HDL Student Edition
20x

(2) Simulation capacity limitations compared to full commercial release of Active-HDL. If limit is exceeded, simulation speed drops to numbers specified below.
Capacity Restrictions
Capacity
Slow down
Instance Limit EDU Edition
20,000
20x
Instance Limit Student Edition
500
100x