Configurations News Training Contact Sales FPGA Design Creation and Simulation Active-HDL™ is a Windows® based, integrated FPGA Design Creation and Simulation solution for team-based environments. Active-HDL’s Integrated Design Environment (IDE) includes a full HDL and graphical design tool suite and RTL/gate-level mixed-language simulator for rapid deployment and verification of FPGA designs. The design flow manager evokes 120+ EDA and FPGA tools, during design entry, simulation, synthesis and implementation flows and allows teams to remain within one common platform during the entire FPGA development process. Active-HDL supports industry leading FPGA devices from Altera®, Atmel®, Lattice®, Microsemi™ (Actel), Quicklogic®, Xilinx® and more. Top Features and Benefits Project Management Unified Team-based Design Management maintains uniformity across local or remote teams Configurable FPGA/EDA Flow Manager interfaces with 120+ vendors tools allows teams to remain on one platform throughout FPGA development Graphical/Text Design Entry Quickly deploy designs by using Text, Schematic and State Machine Distribute or deliver IPs using more secure and reliable Interoperable Encryption standard Simulation and Debugging Powerful common kernel mixed language simulator that supports VHDL, Verilog, SystemVerilog(Design) and SystemC Ensure code quality and reliability using graphically interactive debugging and code quality tools Perform metrics driven verification to identify unexercised parts of your design using Code Coverage analysis tools Improve verification quality and find more bugs using ABV - Assertion-Based Verification (SVA, PSL, OVA) Connect the gap between HDL simulation and high level mathematical modeling environment for DSP blocks using MATLAB®/Simulink® interface Documentation HTML/PDF Abstract design intelligence and represent them in easy to understand graphical form using HDL to schematic converter Share designs quickly with auto-generate Design Documentation in HTML and PDF