Helpful Aldec Design and Verification Blog Articles from 2015

Date: 2015/12/21Type: Release

Henderson, NV – December 21, 2015 – Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification solutions for SoC and ASIC designs, publishes a weekly Design and Verification Blog covering news, popular methodologies, and helpful tips and features authored by our top engineers and guest authors. Below are some of the top-viewed and most helpful articles from 2015.

FPGAs Cross Scale Threshold to Enable True FPGA-based Verification

Guest Blog by Doug Amos, One-Man-Army FPGA Consultant

U.V.M. Spells Relief

Create robust test environments with ease

Putting the “Automation” back into EDA

The Pythonic Tonic: Miracle cure or Snake-oil?

Xilinx Tcl Store Integrates Aldec Simulators with Vivado IDE

App now integrates Active-HDL & Riviera-PRO

Scaling the “Internet of Things”

With Aldec HES-DVM™

Helping FPGA Designers get started with UVM

Guest Blog by Doulos CTO, John Aynsley

The Problem with CDCs

And how it affects your DO-254 project

For more on Aldec’s helpful solutions, visit or email


About Aldec

Established in 1984, Aldec is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Emulation, Design Rule Checking, Clock Domain Crossing, VIP Transactors, Requirements Lifecycle Management, DO-254 Functional Verification and Military/Aerospace solutions.


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Media Contact: Aldec, Inc.                               
Christina Toole, Corporate Marketing Manager
+ (702) 990-4400

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