This document describes how to start the Active-HDL simulator from Xilinx Vivado to run behavioral and timing simulations. This application note has been verified on Active-HDL 13.0 and Xilinx Vivado 2021.2. This integration allows users to run VHDL, Verilog, Mixed, and SystemVerilog (Design) simulations using Active-HDL as the default simulator.
Set the path to the Active-HDL installation directory in the 3rd Party Simulators category by going to Tools | Settings | 3rd Party Simulators. Alternatively, add the Active-HDL installation directory to the PATH environment variable. The settings from the Vivado environment take precedence over the path specified in the environment variable.
Note: If Vivado is already running while you modify the PATH environment variable, then you will have to restart Vivado to have your new PATH variable effective inside Vivado.
In order to run the simulation successfully, depending on the design, both VHDL and Verilog simulation libraries for the respective Xilinx Vivado version may have to be installed in Active-HDL. You can check which libraries are currently installed in your Active-HDL version using the Library Manager tool. The tool can be accessed by selecting the View menu and then Library Manager. Libraries have to be compiled for the Active-HDL version you are using for simulation.
You can compile Xilinx libraries from sources with the Compile Simulation Libraries option from the Vivado Tools menu or the compile_simlib -simulator activehdl command.
Note: After generating the compiled libraries from Xilinx, they have to be attached to Active-HDL environment. For more information refer to Compiling Xilinx Vivado Simulation Libraries for Active-HDL.
You can also install precompiled libraries:
If you have received a web link to download Active-HDL, on the same page you will find the links to download Xilinx libraries.
At any time you can visit the Update Center to download the latest Xilinx libraries at https://www.aldec.com/en/downloads.
Create or Open a project in Xilinx Vivado Project Manager.
Select the Settings tab from the Flow Navigator pane.
Under the Simulation category of the Settings window, change the Target Simulator to Active-HDL Simulator.
The libraries used in the project should be specified either in the Active-HDL or Vivado environments. For details, refer to Compiling Xilinx Vivado Simulation Libraries for Active-HDL.
Here under the Compilation tab, you can enable a range of the Verilog and VHDL compiler features such as the coverage analysis and debug mode or assign values to generics/parameters. The generics/parameters can be set in the Generics/Parameters options field whereas the features can be selected from the list of available compiler options.
Note:You may need to select the activehdl.compile.vhdl_relax check box that relaxes some LRM requirements when compiling VHDL files.
Under the Elaboration and Simulation tabs you can set simulation related arguments e.g. logging all signals to simulation database, accessing signals for waveform, simulation run time.
Once all options are set according to your requirements, click OK.
Note: If a version of Active-HDL was updated between subsequent simulation runs, you should clear the Enable incremental compilation option available in the Advanced tab of the Simulation category to remove the files compiled with previous version of Active-HDL.
Now, click on the Run Simulation item in the Flow Navigator pane and select the type of simulation you want to run. This will run the simulation in the GUI mode.
Alternatively, you can run the simulation using the Console (VSimSA) mode. To do so, type the following commands in the Vivado Tcl Console window:
launch_simulation -batch -install_path <path>
Vivado generates DO macro scripts for compilation and simulation based upon the settings you provided in the above steps and stores them in the <project_dir>\<project_name>.sim\<simulation_set>\<simulation_type>\activehdl directory.
The compilation macro (<name>_compile.do) sets up the working libraries to which the design will be compiled, maps the Xilinx Vivado libraries, and runs the compilation with the options specified in Project Settings | Simulation | Compilation.
The simulation macro (<name>_simulation.do) initializes and runs the simulation session while recording the signal history to the simulation database (ASDB).
The Aldec's compiler executes the compilation macro in the Console regardless of the selected mode. The compiler output is redirected to the Vivado Tcl Console window.
If compilation is finished successfully, Active-HDL is launched and the simulation macro is executed. The macro initializes and runs the simulation session while recording the signal history to the simulation database (ASDB). In the GUI mode before initializing simulation, the macro creates and opens the design and then maps the default library specified in the General category of the Vivado Settings window. When the simulation is completed, the history of signals is presented in the Waveform Viewer. At that point, you can navigate through the history of the Console window using the arrow keys and relaunch any command from the simulation macro. To browse the design sources, use the View source: <item>, View Generated Code, or View Declaration option from the context menu of the Structure tab of the Design Browser window. In the Batch mode in turn, there is no design creation and default library mapping. The simulator output is redirected to Vivado Tcl Console and VSimSA is closed after simulation completion.
The export_simulation command allows you to export the compilation and simulation macros generated by Vivado to the directory specified with the -run_dir argument. The macro to be exported is denoted with the -mode and -type arguments.
Specifies the directory to which the macros selected with the -mode and -type arguments will be exported.
Specifies the directory containing the precompiled simulation library.
Sets the simulation mode. The following modes are allowed: Behavioral, Post-synthesis, and Post-implementation that can be selected with the behavioral, post-synthesis, and post-implementation parameters, respectively.
Specifies the netlist type. The allowed values are functional and timing. This argument is only applicable when the selected simulation mode is Post-synthesis or Post-implementation (post-synthesis or post-implementation passed to -mode).
Suspends displaying of error messages reported by the command.
Suspends limiting of messages displayed in the console during the command execution.