Scalable HES™ Prototyping Platform

Aldec HES™ Prototyping Platform provides SoC/ASIC hardware and software developers with a high quality FPGA based HES boards utilizing the latest and largest FPGA chips - currently Xilinx® Virtex7® or UltraScale® families. It consists of large capacity multi-FPGA boards and is scalable from 8 to 633 Million ASIC gates by using backplane boards with fully utilized LVDS and GTH/GTX interconnections. Thus, it is ideal either for pre-silicon integration of the complete SoC or verification at the sub-system level.

The HES prototyping solution was architected to provide easy implementation and expansion while sustaining the highest performance and clock speeds sufficient for firmware and software development, debugging and SoC bring-up for all layers of the software stack including Android, Linux, Windows or RTOS operating systems and user level applications.

 

SoC Prototype Extension with Daughter Cards

The HES Prototyping Platform capabilities are extended with the rich portfolio of Daughter Cards that utilize high speed connectors which are either standard FMC HPC or BPX off-the-shelf MOLEX parts. Due to the use of non-proprietary connectors the daughter cards can be reused across different hardware platforms.

 

Each daughter card provides a unique set of devices and peripherals relevant to a given application, for instance:

 

Key Features & Benefits



Printed version of site: www.aldec.com/en/solutions/prototyping/hes_prototyping