Multi-FPGA Design Partitioning

Due to the size of today’s SoC designs, the prototyping boards must contain multiple, large FPGA devices that are scalable (or expandable). Selecting the appropriate FPGA prototyping board and design partitioning solutions are among the challenges many teams are facing today. Not only the design has to be split into blocks so that each of them matches one FPGA, but also the user has to arrange interconnections between them using physical I/Os and traces available on the board. The physical interconnections of an example 633 Million ASIC gates design implemented in HES™ Prototyping Platform (with backplane) is indicated in the picture below.

 

multi-fpga-design-partitioning

 

The number of physical I/Os and traces is always scarce, and does not keep pace with the growing FPGA size. High speed serial I/O and LVDS transmission capable I/Os compensate for this limitation but that means the user of the FPGA prototyping platform has to implement some Time Division Multiplexing (TDM) technique in order to interconnect design partitions on the prototyping board. Another complication is proper distribution of clocks and board-level timing correctness assurance.

 

multi-fpga-design-partitioning

 

All these challenges are addressed with the Aldec HES-DVM software that provides prototyping flow and tools that aid in design partitioning, interconnection, clocks mapping and timing closure.

 

multi-fpga-design-partitioning

 

HES-DVM Proto Key Features & Benefits

○ Use SERDES modules
○ LVDS or single-ended signalling
○ Direct routing or global traces



Printed version of site: www.aldec.com/en/solutions/prototyping/fpga_design_partitioning