ASIC/SoC design verification is a continuous endeavor within the semiconductor industry because the end goal is a moving target, tied to ever-growing chip complexity and increasing density. Reducing the time to design, simulate, debug and cover are the four main objectives of design verification. The solution is fit-for-purpose EDA tools that consist of mixed-language HDL simulation, mixed-signal simulation, DSP co-simulation, integrated and unified visual debugging, assertions, coverage, and static design analysis.
Central to design verification is MDV. This is the cyclic confirmation that the verification plan and its construction, execution and analysis are working together.
MDV is performed to improve the predictability, productivity, and quality of the verification effort. Metrics include code coverage and functional coverage using assertions, SystemVerilog covergroups, OSVVM and FSM coverage, all of which are supported by Riviera-PRO and Active-HDL. Also helping you rise to the design verification challenge is Aldec’s Coverage DataBase (ACDB), our implementation of Accellera UCIS requirements.
Mixed-language simulations tools must support the latest industry verification methodologies in order to employ various verification strategies and maximize reuse. Both Riviera-PRO and Active-HDL support the following verification methodologies.
Static linting performed using ALINT-PRO on RTL code - written in VHDL, Verilog, and SystemVerilog – ensures HDL code robustness by flagging absolute errors and warnings early on in your design flow. Linting helps detect a wide variety of design issues, including poor coding styles, improper clock and reset management, improperly synchronized clock and reset domain crossings (CDC, RDC), simulation vs synthesis mismatches, incorrectly implemented finite state machines (FSM), poor testability, and other typical source code issues throughout the design flow.
ALINT-PRO also supports Phase-Based Linting (PBL), which inserts clear priorities into the design analysis process by reducing the total number of issues to be addressed and minimizing the number of design refinement iterations. PBL speeds up debugging time by 3 to 10x compared to the traditional approach.
Clock Domain Crossing (CDC) and, increasingly, Reset Domain Crossing (RDC) verification is challenging for large, complex designs with multiple clocks and reset lines. ALINT-PRO features an ALDEC_CDC rule plug-in that focuses on clock and reset domain crossings analysis as well as the handling of metastability issues.
ALINT-PRO also provides Design Constraints Support, an invaluable aid to verifying metastability, and static and dynamic verification.
SoC FPGAs present new verification challenges for system, software, and hardware engineers, and many HW/SW integration problems are only found in the testbed; i.e. late in the development lifecycle and with the SoC FPGA running.
Aldec provides a HW/SW co-simulation interface between Riviera-PRO and QEMU, the open-source processor emulator. System integration and co-simulation of HDL code with software applications/drivers executing in QEMU is now simplified with the addition of the Aldec QEMU Bridge; which connects Riviera-PRO and QEMU, and converts SystemC TLM transactions to AXI and vice versa, providing a fast interface for co-simulation.
Metric Driven VerificationUVM Transaction DebuggingUVM, OVM and VMMOS-VVM™Static LintingCDC and RDC VerificationCo-Simulation with QEMU and Riviera-PRO