Airport City, Israel – November 10, 2016 – Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification solutions for system and ASIC designs, will unveil the latest HES-DVM™ software package for emulation and simulation acceleration on HES-7™ and custom, in-house high speed prototyping boards at the SemIsrael Expo.
Aldec distributor, Advanced Semiconductor Technology (AST), will be on hand to demonstrate the new solution at the event to be held in Airport City, Israel on November 15, 2016.
The latest release of HES-DVM delivers a setup flow for Xilinx® UltraScale™ FPGA technology and support for a new HES board: the HES7XUS1320BPX containing three XCVU440 devices on a single PCB with an estimated capacity of 79 Million ASIC gates, an optimal choice for emulation and prototyping of mid-size SoC designs. For larger designs, the system can be scaled up with a backplane that can interconnect up to four boards to provide capacity of 316 Million ASIC gates.
With HES-DVM, the same prototyping board can be reused for simulation acceleration or co-emulation with Virtual Models. The connection with simulators or virtual platforms is based on Accellera’s standard SCE-MI that is a transaction level interface. This HES-DVM release adds support for SV-Connect which was introduced in latest revision of SCE-MI 2.3 to facilitate integration of Function-based transactors with SystemVerilog or UVM testbench. With SV-Connect the C source code for DPI-C functions is generated automatically to save time and increase productivity of verification engineers.
“Verification of complex SoC ASIC designs often implies conflicting requirements. While software engineers require a design prototype running at high clock frequency, hardware designers continue to ask for more and more debug probes and controllability. This is the reason why design houses kept separate platforms – FPGA prototyping for software developers and big-box emulation for hardware verification engineers,” said Krzysztof Szczur, Hardware Verification Product Manager. “Aldec’s HES-DVM is the only solution to such inefficient duplication of hardware resources. Based on our customers’ feedback, we have added the capability to create one design implementation that combines emulation and prototyping clock domains to satisfy the requirements of all teams within a SoC project.”
The latest release of HES-DVM also enables connecting free running and asynchronous clocks to the design implemented in FPGA, a big step forward that enables harmonious co-existence of emulation comprising of comprehensive debugging capabilities and prototyping that achieves significantly higher clock ratios.
HES-DVM 2016.10 is available now. To learn more or to evaluate, please visit Aldec Distributor AST at Booth #38 at the SemIsrael Expo, contact email@example.com, call +1 (702) 990-4400, or contact our worldwide distribution partners.
HES-DVM™ is a fully automated and scalable hybrid verification environment for SoC and ASIC designs. Utilizing the latest co-emulation standards like SCE-MI or TLM and the newest FPGA technology, hardware and software design teams obtain early access to the hardware prototype of the design. HES-DVM is used in labs worldwide for tasks including simulation acceleration, emulation, hybrid virtual prototypes, co-emulation, in circuit emulation, and software validation at MHz speeds. Learn more about Aldec Hardware Emulation Solutions.
Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, , CDC Verification, IP Cores, Embedded, Requirements Lifecycle Management, DO-254 Functional Verification and Military/Aerospace solutions. www.aldec.com
Aldec is a registered trademark of Aldec, Inc. All other trademarks or registered trademarks are the property of their respective owners.
Christina Toole, Aldec, Inc.
+ 1 (702) 990-4400