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FPGAs for Verification, Easier UVM and FPGA-based Acceleration, SoC Verification Made Easy |
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[ON DEMAND WEBINAR] |
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'FPGAs for Verification, UVM Simulation Acceleration with Scalable FPGA Platforms' Presented by Alex Grove, First EDA Most ASIC IP and SoC platforms will be validated at some point using FPGAs; this task is typically referred to as ASIC FPGA prototyping. At the same time, FPGAs are increasingly being used for verification due to the performance and scalability of these systems. |
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[ARTICLE]
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Easier UVM and FPGA-based acceleration work together to increase UVM productivity By Doug Amos, One-Man-Army FPGA Consultant These days, verification of the most complex designs is performed using a standard verification methodology, probably SystemVerilog-based UVM. Many verification teams have ramped up on UVM, but others have yet to take the plunge. Why is that? And how big a “plunge” is it, anyway?
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[WHITE PAPER]*
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SoC verification made easy with Aldec HES-DVM™ By Dawid Grabowski, Aldec As designs grow larger, the time spent verifying a project is growing longer as well. As a solution, some companies are trying to ‘shift-left’ their schedules. Verification via software simulators is not fast enough for large System-on-Chip (SoC) design projects, therefore one option is to use an FPGA emulator to speed up the design process. |
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*Registration required. With an Aldec account you'll have easy, one-click access to event registration, support, product downloads, evaluation licenses, recorded webinars, white papers, and other resources.
Aldec is a global industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, CDC Verification, IP Cores, DO-254 Functional Verification and Military/Aerospace solutions. |
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+1.702.990.4400 |
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