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Name Products Type Action
Debugging SCE-MI Co-Emulation in Riviera-PRO   
Abstract: Debugging a design during emulation with a high level of visibility can be a challenge. This paper presents Aldec’s solution to this problem; a debugging environment for SCE-MI co-emulation that provides 100% signal visibility of the design running in an FPGA-based emulator. Debug probes captured intelligently from emulator retain original signals names and hierarchy paths to provide true RTL view of design in emulation.
Riviera-PRO, HES-DVM ホワイトペーパー
Introducing Transactions In Design Verification   
Abstract: Modern ASIC and FPGA designs can usually be treated as complete systems, not just electronic circuits. Design and verification of those systems typically requires the use of transaction-level descriptions, so enhanced support for transactions in verification tools is critical. This paper describes basic transaction related terms and the new transaction recording and visualization solution available in Riviera-PRO™ simulator.
Riviera-PRO ホワイトペーパー
Making Floating-Point Arithmetic Work in Your RTL Design   
Floating-point arithmetic becomes a widely used format in digital system design. For example, DSP applications often demand high precision while operating with large dynamic ranges. The IEEE 754™-2008 floating-point arithmetic standard fulfills this criterion but it might be extremely hard to comprehend and use. This document discusses challenges associated with debugging floating-point arithmetic designs and explains how to tackle them using the tools available with your floating-point aware IDE.
Riviera-PRO ホワイトペーパー
Meeting Growing Verification Demands   
Abstract: The first decade of the 21st century brought tremendous growth of the size of typical digital design, triggering growing demands for faster, safer and more thorough verification. In response to those demands, many new flavors of verification were invented and implemented in the tools, making engineers face difficult choices. This paper gives detailed overview of currently available verification methodologies suitable for large designs and shows how Aldec tools can help in their implementation.
Riviera-PRO, ALINT, HES-DVM, HES-7 ホワイトペーパー
Randomization and Functional Coverage in VHDL   
Abstract: Modern digital designs reach the scale of complete systems and require support of Constrained Random Test and Functional Coverage in verification. Although VHDL does not have built-in, direct support for those methodologies, there are neat solutions that allow their quick implementation in your testbench.
Active-HDL, Riviera-PRO ホワイトペーパー
RTLとネットリストの等価性の達成:リントは必須!   
シミュレーションと論理合成のミスマッチの問題は、物理デバイスの誤動作を引き起こす可能性があります。RTLシミュレーションで機能的に完璧であっても、物理的な実装で重大なデザインバグが含まれている可能性があります。RTLリントは、シミュレーションと論理合成のミスマッチ問題を特定して修正する唯一の方法です。本紙では、シミュレーションから論理合成への典型的なミスマッチ問題を簡単な例で示します。 記載されている問題ごとに、リントチェックで確認され、説明されます。
Active-HDL, Riviera-PRO, ALINT-PRO ホワイトペーパー
Synthesis of energy-efficient FSMs implemented in PLD circuits   
Abstract: The paper presents an outline of a simple synthesis method of energy-efficient FSMs. The idea consists in using local clock gating to selectively block the clock signal, if no transition of a state of a memory element is required. The research was dedicated to logic circuits using Programmable Logic Devices as the implementation platform, but the conclusions can be applied to any synchronous circuit. The experimental section reports a comparison of three methods of implementing sequential circuits in PLDs with respect to clock distribution: the classical fully synchronous structure, the structure exploiting the Enable Clock inputs of memory elements, and the structure using clock gating. The results show that the approach based on clock gating is the most efficient one, and it leads to significant reduction of dynamic power consumed by the FSM.
Riviera-PRO ホワイトペーパー
Those Pesky Interfaces…   
SystemVerilog interfaces offer some very interesting features for both hardware designers and verification engineers. Unfortunately, they are also one of the most misunderstood SV constructs. This document tries to explain interfaces, paying special attention to the virtual interface concept used in popular UVM library.
Riviera-PRO ホワイトペーパー
Using Plots for HDL Debugging as a Powerful Alternative to Traditional Waveforms   
The most commonly used approach to analyzing objects in an HDL design, is based on the well-known digital waveforms available with any commercial simulator today. Such a time domain representation of data with respect to time, allows verifying many parameters of a designed digital system, but it may not be efficient for applications such as image processing, digital filter design, embedded system design, and others. This document presents Plot, a new solution for a graph-based analysis of HDL objects, correlations between them, and a number of practical applications for it.
Riviera-PRO ホワイトペーパー
Verification of Multirate Systems with Multiple Digital Blocks   
Modern RF system designs require extensive digital signal processing and flexibility to fulfill the current and coming standards. Systematically growing set of functions implemented on SoC pushes system architects and hardware designers to look for methodologies, which would enable efficient co-design and co-verification. In this paper, we will be discussing the challenges associated with simulating multirate system-level designs that include multiple digital blocks.
Riviera-PRO ホワイトペーパー
Xilinx Zynq-based Development Platform for ADAS    
ADAS is an essential step between initial DA (Driver Assistance) systems and fully autonomous cars capable of driving without human guidance. Aldec provides an FPGA-based development platform powered by Xilinx Zynq-7000 SoC/FPGA heterogeneous technology, as well as a set of ADAS-class reference designs for rapid development of current and next-generation ADAS solutions for the automotive market.
Riviera-PRO, TySOM™ EDK ホワイトペーパー
大容量FPGAデバイスの最適設計手法   
最新のFPGA技術の進歩と大規模FPGAデバイスのリリースにより、デザインチームは高品質のHDLコードを作成する際に今まで以上に多くの課題に直面しています。機能検証と実装段階で時間を節約するためには、デザインプロセスの初期段階から設計の品質を確保することがますます重要になります。ASICの設計フローでは、Lintツール(デザインルールチェッカーと呼ばれることもあります)は、設計ライフサイクルの初期段階で設計品質を保証し、プロジェクトライフサイクル全体にわたってこの品質を維持します。
Riviera-PRO, ALINT-PRO ホワイトペーパー
12 results
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