Getting Started with Active-HDL in Diamond


This tutorial provides instructions for using Active-HDL in Diamond. Active-HDL is an integrated environment designed for development and verification of VHDL, Verilog, System Verilog, EDIF, and System C based designs. In this tutorial we use a sample VHDL design provided by Lattice Diamond to perform design entry and simulation.

Getting Started

You will first need to install Lattice Diamond Design Software and the latest version of Active-HDL to be able to successfully complete this tutorial. The free downloads are available here: Active-HDL and Lattice Diamond. You will then need to request a license to run the Diamond Design Software and request an Aldec license.

Creating Workspace and Design

At the start page of the Lattice Diamond, you will be able to create a new Project.

Creating/Adding Files to Design

Creating HDL Source Code

Specify Path to Design



Waveform Viewer

By default, the Accelerated Waveform Viewer is enabled and an *.asdb simulation database is created upon initialization of simulation. The Accelerated Waveform Viewer should be the preferred choice for designers working with large amounts of simulation data. It is optimized for large designs and long simulation runs.

PAUSE/End Simulation

Saving the waveform file for off-liine viewing

You must stop the simulation before saving by clicking End Simulation from the Simulation menu.


Within the tool

Go to menu Help | Product Help to learn more about Active-HDL.

Help on web

Go to Aldec Support to access the online database and other technical documents about Active-HDL.

Support Account

Register or use your Aldec support account at to open a support case or download the software.

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