This application note describes how to start Riviera-Pro as default simulator in Xilinx ISE. This enables Xilinx ISE users to run VHDL and Verilog simulation using Riviera-PRO. This application note was created with Riviera-PRO 2016.10 and Xilinx ISE 14.7. Follow the four steps below to launch Riviera-PRO simulation from Xilinx ISE.
Install Xilinx libraries in Riviera-PRO
Point to the riviera.exe executable file in Xilinx ISE preferences
Set user defined simulation preferences in Xilinx ISE
Run simulation from Xilinx ISE
In order to run simulation successfully, depending on the design, either VHDL or Verilog libraries need to be installed in Riviera-PRO. You can check what libraries are currently installed using the Riviera-PRO Library Manager window. You can access the Library Manager from the menu View | Design Management Windows - Library Manager (Alt+2) as shown in Fig 1.
Figure 1 Library Manager
If you do not have Xilinx libraries (by default Riviera-PRO installs only with the standard libraries), you can either:
Download the precompiled libraries from Riviera-PRO’s download page from the Support Portal (either registration or account is required). You can only download the latest version of Xilinx libraries compile for Riviera-PRO.
In the design tab of the Xilinx ISE, select Simulation, click on the design, and expand the Design Utilities option. Right-click on Compiile HDL Simulation Libraries and select Process Properties. Set library simulator to Riviera-PRO mixed, and set the path to the installation directory of Riviera-PRO (C:\Aldec\Riviera-PRO <version>\bin) as shown in Fig 2. You can check different boxes for different libraries depending on your design. When you are done setting process properties click Apply and OK. Now double click on Compile HDL Simulation Libraries and wait for compilation to end successfully. Then you can go to Riviera-PRO Library Manager and add library using Attach Library button in the top left corner.
Note: Please be sure that you are using the correct libraries. Users with 64-bit should download the 64-bit libraries. Users with 32-bit should download the 32-bit libraries.
Figure 2 Process Properties for Compiling needed Libraries
In order to run Riviera-PRO from ISE Project Navigator, you need to define it as a default HDL simulator in Xilinx environment.
Open your Xilinx project in Xilinx Project Navigator and open the preference window (Edit | Preferences...).
In the Preferences window, go to ISE General | Integrated Tools, and as shown in Fig 3, point to the riviera.exe file, in the Model Tech Simulator box. The file is located at C:\Aldec\Riviera-PRO <version>\bin\.
Note: If the Model Tech Simulator field is pointing to another path (e.g. Xilinx.bat), click on Default to clear the field and then select the riviera.exe file.
Then click Apply and OK to close the Preferences window.
Figure 3 Preferences - Integrated Tools Options Window
In the Design Tab of Xilinx ISE Project Navigator select Simulation as shown in Fig 4.
Then from the drop down menu select Behavioral as shown in Fig 4.
Figure 4 Setting the Simulation Flow in Design Tab
Next, depending upon the HDL language of your design, right-click your design, select Design Properties, and set the simulator to Modelsim-SE mixed as shown in Fig 5.
Figure 5 Selecting Simulator in Design Properties Tab
Now in the Processes window right click on the Simulate Behavioral Model and click on Process Properties as shown in Fig 6.
Figure 6 Open Process Properties from Process window
When Process Properties dialog box opens, select Simulation Properties and make following changes as shown in figure 7. Make sure that Property display level at the bottom of the dialog box is set to Advanced.
Add -o2 +access +r in Other VSIM Command Line Options under property name.
Vendor libraries can be made visible during compilation and simulation using -L <library_name> option in Other VLOG Command Line Options and Other VSIM Command Line Options respectively.
Figure 7 Setting Simulation Properties under Process Properties
Next, click on the Display Properties category and disable all available properties as shown in figure 8.
Figure 8 Setting Display Properties in Process Properties Window
Then click OK to close the Process Properties - Simulation Properties dialog box.
To start the Riviera-PRO simulator right-click on Simulate Behavioral Model in the Design tab and select the Run option (figure 6) from the pop-up menu.
When Riviera-PRO is launched, the following files will be displayed in the Files tab of the Design Browser window:
HDL source files
Script file (top_level.fdo), that is used to automatically run compilation and simulation. The toplevel.fdo file is generated by the Xilinx ISE Design Suite. (Depending on a simulation stage, additional scripts files can be also generated, i.e. *.udo, *.ndo, *.mdo, or *.tdo.)
Then Riviera-PRO automatically proceeds to execution of commands specified in the script, i.e. it compiles all design files, initializes the simulation session, and runs simulation for the user-defined time specified in the Simulation Run Time field of the Process Properties - Simulation Properties dialog box in Xilinx ISE (figure 7).
You may sometimes need to edit the script and add additional commands. All the generated scripts can be opened and edited in the built-in Riviera-PRO text editor. Note however that some of these files (including toplevel.fdo) are overwritten each time you initialize the simulation session from ISE Project Navigator. Thus instead of editing the toplevel.fdo script, it is recommended to add all user-defined commands to additional scripts (e.g. toplevel_wave.fdo or toplevel.udo) that are not automatically overwritten whenever a new session starts. These scripts can be called while executing toplevel.fdo. After you complete all modifications, you can execute the script file(s) in the command line, e.g. issuing the following command in the Console window: do testbench.fdo
First, verify that the library simprim is installed in Riviera-PRO. You can download the latest libraries from the Support Portal.
In Xilinx, switch the Design Tab from Simulation to Implementation.
Figure 9 Implementation in Design View
Run the synthesis and implementation process. Be sure to expand the Implement Design process and run the Generate Post-Place & Route Simulation Model process.
Figure 10 Run Synthesis and Implementation Processes
Switch the Design View to Simulation and change the drop-down box from Behavioral to Post Route.
Figure 11 Post-Route Simulation
Right-click on Simulate Post-Place & Route Model in the processes window and select Process Properties.
You can observe the additional field Delay Values To Be Read from SDF, this indicates an SDF was created to run a timing simulation.
Figure 12 Process Properties for Timing Simulation
The Display Properties should remain the same as the previous simulation.
Under Simulation Model Properties you can also observe the -sdf switches used for the timing simulation.
Figure 13 Simulation Model Properties
Run the simulation by right-clicking on Simulate Post-Place & Route Model and select run.