Xilinx コンストレイントを Active-HDL で使用する方法


本アプリケーションノートは3つの部分に分けられます。最初の部分では、スケマティックタイプ(EDIF)のデザインにおいて、コンストレイントを与える時の手順を説明します。2番目の部分では、VHDLやVerilogソースファイルにおいてコンストレイントを与える手順を説明します。3番目の部分では、デザインのインプリメンテーション時に、Xilinx コンストレイントエディタをどのように使用するかを説明します。

本アプリケーションノートをできるだけ簡潔にするために、Active-HDLで使用する一般的な Xilinx コンストレイントだけを表示します。Xilinx コンストレイントの詳細については、Xilinx ドキュメント CD のコンストレイントガイドマニュアルを参照してください。Xilinx ドキュメント CD は、Foundation や ISE などの Xilinx パッケージに含まれています。またコンストレイントガイドマニュアルは Xilinx オンラインヘルプでも利用可能です。


  1. schematic_constr.zip file を解凍後、schematic_constr.adf プロジェクトを開きます。Active-HDL が起動され、デザイン全体が開きます。デザインは 3つの段階を順次動作する64-bit 幅のコンパレータです。本デザインのブロック図を図1に示します。3つの動作段階のタイミングを図2に示します。

    図1: コンパレータのブロック図

    The data is latched before comparison as shown in the timing diagram below.

    図 2: コンパレータの動作タイミング

  2. After opening the schematic_constr design, you should see the design and all of its components in the Design Browser as shown in figure 3:

    Figure 3: Files list of comparator design

  3. Next, double-click on comparator.bde to open the top-level schematic of the design. The content of the file is displayed below.

    Figure 4: Top-level schematic of comparator design

    As you may have noticed, several constraints are already assigned to several objects of the schematic file. These constraints on a schematic sheet are referred to as parameters. Parameters correspond to constraints that are instructions assigned to objects such as symbols, nets, or ports on an FPGA or CPLD schematic to indicate their timing, placement, grouping, and other characteristics. This information is used by the implementation software during technology mapping, placement and routing.

    This design implements several examples of different constraints applied as parameters to the different objects. Let us look at these examples.

    First, we will examine the pin location constraint assigned to the buffers in the design. The LOC constraint gives the user the possibility to specify explicitly the location of different primitives in Xilinx FPGA or CPLD. Especially, user can associate given ports with given pins of the FPGA package by locating input or output buffers of the given IOB block. We decided to implement this design in Virtex XCV50CS144.

    As it was mentioned, applying constraints can be done by defining parameters. This procedure was illustrated on the example of the CLK port buffer.

  4. To assign parameters to the object, simply right-click the object and then select the Properties option from the pop-up menu. The Symbol Properties window of the object will be invoked. In the Parameters tab, you can specify the name of the attribute and its value. The example of the selected buffer shown below initializes the attribute?s name in the Name column to LOC and its value to K7.

    Note that you should check the Parameters option in the View Text tab of the Symbol Properties dialog window to make all parameters visible in the schematic.

    Figure 5: Viewing constraints in Symbol Properties window

    Similarly, the same operation was done for other ports (buffers) in the design. Note that there is one input bus Din(63:0) that uses input buffers that are grouped in a special component ibuf64 (instance U9). This component is composed of separate input buffers. You can see that by double-clicking on the U9 instance. Note that the LOC constraint is assigned separately to each buffer.

    Figure 6: LOC constraints of Din(63:0) input bus

    In the same way, you can assign other constraints. For some ports in the design, the PULLUP = true constraint has been defined, which indicates that such a port connects pull-up resistor after the configuration of the FPGA device. This parameter can be assigned both to the scalar port and to the bus as well.

    Figure 7: PULLUP constraint of CEin and Din(63:0) input ports

    In another example, we assigned the constraints INIT = 0 and IOB = true to the FDCE flip-flop. INIT defines the initialization value of the flip-flop after powering on the FPGA. The second constraint IOB is a mapping constraint that manages the placement of the flip-flop in the IO block of the FPGA.

    Figure 8: INIT and IOB constraints of FDCE flip-flop

    Grouping and timing constraints are the special types of constraints used to define timing requirements for the design.

    The grouping constraints like TNM or TIMEGRP are used to identify elements to make up a group that can be used in the timing constraints specification TIMESPEC. For more information about these kind of constraints, refer to the Xilinx Constraints Guide.

    It is possible to specify groups and timing constraints immediately from the Active-HDL schematic during the design entry stage.

    Let us look at the block diagram representation again. As you can see, there is an identified critical timing path that starts from registers regA and regB and ends in register Reg. The comparator makes this path critical in timing performance.

    Figure 9: Critical paths of comparator design

    In order to specify the timing constraints, first groups of points at the beginning of the path and at the end should be defined. While defining the TNM parameter for each register, you can specify the groups. The procedure of defining TNM is the same as previously described for other constraints ? by assigning parameters TNM to the registers.

    Figure 10: TNM parameter assigned to U2 instance

  5. Invoke the Symbol Parameters dialog for the U2 instance (i.e. right-click the symbol and choose Properties from the pop-up menu). In the Parameters tab, you will see how the TNM grouping constraint was defined.

    Note that the reg64 register is composed of primitive flip-flops. To examine this, simply double-click the symbol to go through the hierarchy.

    When you establish the TNM for the symbol, then all internal flip-flops of this symbol are assigned to the start_criticalA group. It means that outputs of all these flip-flops are in that group.

    The start_criticalA group defines the starting points of the critical timing path. In the same way, we defined other groups ? start_criticalB and END_CRITICAL.

    Figure 11: Critical paths defined in the schematic

    The Xilinx Constraints Guide describes also another grouping constraint referred to as TIMEGRP. It is also possible to define groups with this constraint in Active-HDL.

    In order to create groups with TIMEGRP, simply put the special TIMEGRP symbol from a given library in your schematic sheet (in this example, e.g. from the unisim or ovi_unisim library).

  6. Select the Symbols Toolbox as shown in the figure below, right click and choose Select Libraries.

    Figure 12: Opening the BDE Symbols Toolbox

  7. Select the XILINX unisim library as shown in the figure below and click OK.

    Figure 13: Library Selection

  8. Place the TIMEGRP symbol on the schematic by dragging it as shown below.

    Figure 14: Placing TIMEGRP symbol in the schematic

    When you have instantiated the TIMEGRP symbol on your schematic, you can define new groups.

    In order to illustrate this, we created START_CRITICAL group that is composed of two other groups, defined earlier by TNM constraint: start_criticalA and start_criticalB.

    A definition of this new constraint was done in the same way as the others from this design by using the Parameters dialog box for the TIMEGRP symbol.

    Let us right-click on the TIMEGRP symbol and choose Symbol Properties from the pop-up menu.

  9. Select TIMEGRP and right-click so as to select Properties as shown in the figure below.

    Figure 15: Select TIMEGRP on schematic to display symbol Properties

    In the Parameters tab, you can see that a new group was defined as a parameter. The name of that parameter is simply the name of the new group START_CRITICAL, and as for the value, there are all groups listed which will render the new group. Note that colons separate all elements in the Value field.

    Figure 16: Definition of START_CRITICAL parameter

    After we have done some group definitions, we can specify some timing requirements to the design. Let us assume that the worst delay of the critical path from registers U2 and U3 through comparator U1 to register U5 is max 13ns.

    In order to define the constraint, user can use another special symbol from the library called TIMESPEC. The TIMESPEC symbol with defined parameters is shown in the figure below.

    Figure 17: Parameters of TIMESPEC symbol

    Note that all the TIMESPEC constraints can be defined as the parameters of the TIMESPEC symbol as described earlier. There is only one thing worth to emphasize, namely the syntax of this constraint. As you can see, all the names of timing constraints start with TS (this is defined by the Xilinx Constraint Guide and is required to be properly interpreted during the implementation process). In the Value field, the keywords FROM and TO indicate the start and end point of the constrained path.

    For the start and end points, we used groups of flip-flops; that was defined earlier, namely START_CRITICAL and END_CRITICAL. The specification of the timing constraint should be similar to presented in the following table.

    Table 1: Definition of TS_critical timing constraint

    Two more timing constraints were also defined: TS_CombIn and TS_CombOut. They specify timings for inputs and outputs. To define these constraints, predefined groups FFS and PADS were used. FFS-group means all flip-flops in the Implementation and PADS means all pads used in the design. The definition of TS_CombIn and TS_CombOut is shown in the table below.

    Table 2: Definition of TS_CombIn and TS_CombOut timing constraints

    HDL Design Entry

    Xilinx supports constraints entry for VHDL and Verilog.

    In VHDL source files, user can describe constraints in the form of attributes. Before any attribute is specified, it should be declared first. The syntax of a constraint declaration in VHDL is as follows.

    attribute attribute_name : string;


    attribute RLOC : string;

    Note that for the purpose of specifying constraints, the attribute of type string is used.

    You can declare the attribute in the entity or architecture. When declared in the entity, it is visible in both the entity and architecture body but when declared in the architecture, it cannot be used in the declarative part of the entity.

    When you have declared the attribute, you can specify constraints with the syntax given below:

    attribute attribute_name of {component_name|label_name|entity_name|signal_name |variable_name|type_name}: {component|label|entity|signal|variable|type} is attribute_value;

    You can also specify constraints in Verilog source files. There is no attribute mechanism in Verilog similar to VHDL but synthesis tools can recognize some directives provided as comments.

    The synthesis constraints are indicated by the keywords synthesis attribute placed in a commented line. The full syntax is as follows:

    //synthesis attribute attribute_name [of] {module_name|instance_name|signal_name} [is] attribute_value;

    Note that all synthesis attributes should be specified in one comment line.


    // synthesis attribute RLOC of u123 is R11C1.S0;

    // synthesis attribute HU_SET u1 MY_SET;

    For the list of supported VHDL and Verilog constraints, see Xilinx Constraints Guide.

    NOTE: There is one inconvenience while employing constraints directly in HDL source files. Not all constraints can be specified in this way and different synthesis tools recognize different constraints that use different syntax. We recommend using a dedicated tool for constraints creation, e.g. Constraint Editor of the Xilinx Implementation Package such as Foundation or ISE.

    The next section describes how to use Xilinx Constraints Editor from the Active-HDL design flow.

    After you have fully developed and functionally verified your design, you can start the implementation process.

    The Design Flow Manager of Active-HDL simplifies the implementation process by integrating all required tools into one application. Before you start the implementation, make sure that all options are properly defined.

    Figure 18: Specifing UCF file in the Implementation Options window

    There is one important aspect to notice about constraints. On the Main tab of the Implementation Options window, there is a section where user can specify a UCF file with constraints defined.

    UCF stands for User Constraint File. It is a text format file that defines all the constraints in your design.

    It is possible to apply the user constraints file to the design immediately from the Design Flow Manager.

  10. To do this, simply uncheck the option Use Default UCF File and click the Browse button to specify the path to the exisiting UCF file.

    For users who do not know the syntax of the UCF file, the best way is to use the Xilinx Constraints Editor. This is the goal of this application note.

  11. When you have defined all options, click OK in the Implementation Options window.

  12. To check the path to Xilinx ISE, click the Flow Settings button in the Design Flow Manager window. If it is not defined automatically, select the name of the tool from the Tool name list box and set the path to its program files.

    Figure 19: Settings for implementation tool in the Flow Configuration Settings window

  13. Now, you are ready to implement the design. Click on the Implementation button in the Design Flow Manager window to start the implementation process.

    The Xilinx Implementation window will be invoked. Note that right after the Translate stage of the implementation is completed, you should abort the implementation. This does not mean that you need to abort the implementation every time your design uses constraints. We are merely suggesting that you do this because the Translate stage is the only stage needed in the implementation process to invoke the Xilinx Constraints Editor (XCE).

    Figure 20: Translate stage in the Xilinx Implementation window

  14. Abort the implementation process after the Translate stage is completed. Then minimize the Xilinx Implementation window and go back to the Design Flow Manager. Click on the Tools button. The window with several Xilinx Design Entry Tools will be invoked. Click on the Constraints Editor icon.

    Figure 21: Launching Constraints Editor in the Design Flow Manager

    The Xilinx Constraints Editor window will be invoked.

    Xilinx Constraints Editor is a tool used for entering almost all constraints defined by Xilinx Constraint Guide. The GUI of the editor simplifies entering the constraints by guiding you through the constraint creation without having to understand the UCF syntax. The Constraints Editor interface consists of a main window, four tab windows (Global, Ports, Advanced, and Misc), the Constraints window, the output window, and numerous dialog boxes. For the detailed description of these windows, refer to the online help of Xilinx Constraints Editor.

    Figure 22: Xilinx Constraints Editor window

    After the constraints have been created or modified within the Constraints Editor, the implementation must be restarted again before the newly created/modified UCF file is used.

    We will just do that but first, we will briefly focus on the abilities of Constraints Editor.

  15. In the Global tab, we can specify timing requirements for all global nets. In our design, we have only one global net. This is the clock signal that was passed through the global clock buffer bufg. Let us specify the required period of that clock with XCE. To do this, double-click on the Unconstrained Clocks clock signal of CLKin. The dialog box presented below will open.

    Figure 23: Clock signal definitions

  16. Set the clock period to 15ns and then click OK.

    Figure 24: Clock Period Set

    Note that each constraint you add or change is simultaneously updated in the Signals with Constraints window of the Editor as shown in the figure below. This will be also written in the UCF file when you close XCE.

    Figure 25: Signals with Constraints window of the Xilinx Constraints Editor window

    With the Xilinx Constraints Editor, user can establish many other constraints. When you switch your view to the Inputs tab, you will see the window similar to the figure below. Here you can provide a bunch of constraints for all ports of your top-level design. The most common are pin locations as well as some timing specifications for ports.

    Figure 26: Inputs tab of the Xilinx Constraints Editor

    There are also Group Constraints and Miscellaneous tabs in the XCE which allow to specify many other constraints like grouping, timing, and other physical ones without knowing UCF syntax.

  17. When you finish working with the XCE, push the Save icon to write your constraints to the UCF file. Note the location of the UCF file via the path displayed as shown below.

    Figure 27: Path for UCF

  18. Ensure that you match the path for the UCF file in the Implementation Options for a "Custom Constraint File" as shown below.

    Figure 28: Path for UCF in Implementation Options

  19. Now, you are ready to restart the implementation process. Maximize the previously minimized Xilinx Implementation window. To restart the implementation, first click on the Back button, and then click on the Play button.

    The implementation tool will recognize newly created UCF for the Translate stage.

    After the entire implementation process is completed, you should then verify whether the constraints have been recognized and applied successfully. You can do this by reviewing reports from the implementation. In order to examine reports, open the Implementation Reports window and click on the reports button near the implementation button in the Design Flow Manager window.

    Figure 29: Xilinx Implementation Complete

    Select the "PAD" report as shown below.

    Figure 30: Invoking Implementation Reports window

  20. Different constraints can be verified in different reports. For example the LOC specification (location of pins) can be checked in the Pad report. Let us open this report to see if the pad locations are the same as defined in the schematic.

    A fragment of this document is presented below. You can see that design was implemented properly, and the constraints provided in the schematic were applied by the synthesis tool.

    Figure 31: LOC constraints in the Pad report

    All the timing constraints can be checked in the Post Layout Timing report. A part of this report is presented below.

    Figure 32: Timing constraints in the Post Layout Timing report

    Note: XILINX no longer supports timing constraints in the BDE

    Information contained in this document has been supplied to Aldec from OEM partners, 3rd party organizations or consultants. All trademarks, registered trademarks and graphical representation of such are property of their respective owners and are used for reference only.

    Online support for your Aldec products is always available at the Support Portal

Ask Us a Question
Ask Us a Question
Captcha ImageReload Captcha
Incorrect data entered.
Thank you! Your question has been submitted. Please allow 1-3 business days for someone to respond to your question.
Internal error occurred. Your question was not submitted. Please contact us using Feedback form.
We use cookies to ensure we give you the best user experience and to provide you with content we believe will be of relevance to you. If you continue to use our site, you consent to our use of cookies. A detailed overview on the use of cookies and other website information is located in our Privacy Policy.