HES-US-440 Prototyping, Emulation and HPC Main Board

Product Description

Capacity

The board HES-US-440 offers a unique combination of Xilinx Virtex UltraScale XCVU440 logic module and Xilinx Zynq-7000 host module featuring ARM dual core Cortex-A9 CPU that allows building a self contained, one-board testbench for the design. It has been optimized for high speed physical prototyping and emulation of medium size ASIC up to 26 Million gates or the largest FPGA designs. The board contains two independent SO-DIMM slots connected to UltraScale that deliver up to 64 GB of DDR4 and two RLDRAM3 modules with SRAM-like interface, low latency and aggregated capacity of 1152 Mb. Such a memory-reach board design makes it applicable for numerous High Performance Computing (HPC) applications apart from physical prototyping. It can be also reused for HES emulation applications like simulation acceleration or co-emulation with virtual models.

Clocking

Very precisely designed clocking block provides 7 regulated any-frequency clock sources and 2 of them are length aligned global clock lines routed to both FPGA devices. The global clock network can be also driven from external sources via dedicated SMA connectors. Complementary to global clocks there are 3 separate clock oscillators dedicated to high speed serial I/O links (GTH, QSFP+, SATA) and 4 oscillators dedicated for using with DDR memories. All on-board clock lines use LVDS signalling to assure high level of signals integrity and immunity to distractions.

Hosting & Interfaces

Due to having of Xilinx Zynq-7000 interface FPGA on the same board with Xilinx UltraScale FPGA it is possible to implement two kinds of hosting applications:

  • Embedded host with Zynq device and embedded Linux booted upon ARM cores running a testbench application that can drive AMBA AXI/AHB bus of the design implemented in UltraScale.
  • External host PC with Zynq device running PCIe-to-AXI bridge connecting a host PC where testbench application is running with the design implemented in UltraScale.

In both cases Aldec provides reusable hardware and software components in the Hes.Asic.Proto utilities bundle. For quick bring-up of embedded host scenario Aldec provides ready to use image of the Linux port for Zynq devices. In case of the external hosting Aldec’s Proto-AXI can be used, which consists of interface module IP with AMBA AXI interface and accompanying PCIe HES driver with high abstraction level C++ API for Linux and Windows PC.

The board provides also a good selection of external interfaces like: PCIe gen3, USB 3.0 and USB 2.0 OTG, UART/USB bridge, QSFP+, 1Gb Ethernet, HDMI, SATA and several flash memories like NAND, SPI and Micro-SD. Other specialized interfaces and devices can be easily added on daughter cards using standard FMC connectors.

BLOCK DIAGRAM

Essential Features

FPGA & Capacity

  • Main FPGA: Virtex UltraScale XCVU440 (A2892 - 1456 I/O, 48 GTH)
    • 26 Million ASIC Gates (estimated for 60% of FPGA utilization)
  • Host FPGA: Zynq-7000 XC7Z100 (FFG900)

Flexible Clocking

  • Total of 18 asynchronous clock generators
  • 7 global clock modules with any-frequency clock synthesizers (Si5326)
    • Base oscillators: 100 MHz, 2x 250 MHz, 2x 300 MHz, 2x 400 MHz
    • SMA connectors for external clocks inputs and outputs
    • 2 of global clocks connected to both UltraScale and Zynq FPGA
      • Low-skew, length aligned clock lines
  • 6 additional oscillators connected directly to UltraScale FPGA
    • 4 separate oscillators dedicated to DDR4 and RLD3 memories (200 MHz)
    • 2 general purpose oscillators 100 MHz, 200 MHz
  • 2 additional oscillators connected directly to Zynq FPGA
    • General purpose oscillators 100 MHz, 200 MHz
  • 3 reference oscillators dedicated to high speed serial I/O
    • 1 GTH reference oscillator: 156.25 MHz
      • routed via fanout buffer (SY89468U) to both FPGAs
    • 1 QSFP+ reference oscillator : 156.25 MHz
    • 1 SATA reference oscillator: 150 MHz
  • 42 clock I/O of UltraScale FPGA available on FMC
  • 13 clock I/O of Zynq FPGA available on FMC

Connectivity & Expandability

  • Daughter card connectors (FMC-HPC)
    • 3 FMC-HPC connected to UltraScale FPGA
      • 480 I/O (240 DIFF) - standard GPIO optimized for LVDS & TDM
      • 26 GTH - high speed serial I/O
    • 1 FMC-HPC connected to Zynq FPGA
      • 144 I/O (70 DIFF) - standard GPIO optimized for LVDS & TDM
      • 4 GTX - high speed serial I/O
  • Inter-FPGA connections
    • 160 I/O (80 DIFF) - standard GPIO optimized for LVDS & TDM
    • 4 GTX - high speed serial I/O

Memory Resources

  • Memories connected to UltraScale FPGA
    • up to 64 GB of DDR4 in 4 SO-DIMM slots (2 independent controllers)
    • 1152 Mb of RLDRAM-3 in 2 modules
    • SPI Flash, NAND Flash
    • Micro-SD slot
  • Memories connected to Zynq FPGA
    • 1 GB of DDR3
    • SPI Flash, EEPROM
    • 2 Micro-SD slots

Interfaces & Hosting

  • Host interfaces connected to Zynq FPGA
    • PCIe x8, Gen 2
    • USB 2.0
    • UART/USB
  • Other peripherals connected to Zynq FPGA
    • I2C peripherals: RTC, Temperature Sensor, Accelerometer, EEPROM
    • Misc: 4 LEDs, 8 Switches
  • Peripherals connected to UltraScale FPGA
    • PCIe x8, Gen 3
    • Gigabit Ethernet
    • QSFP+
    • USB 3.0, USB 2.0 OTG, UART/USB
    • SATA (2 slots)
    • HDMI
    • BullsEye GTH (4 lines)
    • Misc: 11 LEDs, 10 Switches, 60 GPIO in 3 gold-pin connectors
  • Board configuration and FPGA programming
    • Programming from Host
      • via USB 2.0 (Aldec Hes.Asic.Proto application)
      • via JTAG (Xilinx utilities)
      • via Digilent USB JTAG-SMT (Xilinx utilities)
    • Programming from Micro-SD card or QSPI Flash

Ask Us a Question
x

Ask Us a Question

x
Captcha ImageReload Captcha
Incorrect data entered.
Thank you! Your question has been submitted. Please allow 1-3 business days for someone to respond to your question.
Internal error occurred. Your question was not submitted. Please contact us using Feedback form.