Product Description


The board HES-KU115-7Z100 offers a unique combination of Xilinx Kintex UltraScale logic module and Xilinx Zynq-7000 host module featuring ARM dual core Cortex-A9 CPU that enables designing of algorithm accelerators in various scientific and industrial fields. This board has been optimized for High Performance Computing (HPC) applications and prototyping of DSP algorithms thanks to the use of Kintex FPGA module with largest number of DSP blocks in the UltraScale family (#5520 in XCKU115) partnered with 6 external memories that can be accessed simultaneously providing unprecedented aggregated bandwidth. The external memories are 2x DDR4 SO-DIMM supporting up to 32GB of DRAM and 4 RLDRAM-3 modules providing 2.25 Gb of capacity with SRAM-like and low latency interface.

Main FPGA Resources


Logic Cells


Total Block RAM (Mb)


DSP Slices



Very precisely designed clocking block provides 4 regulated any-frequency clock sources and 2 of them are length aligned global clock lines routed to both FPGA devices on board. The global clock network can be also driven from external sources via dedicated MMCX connectors. Complementary to global clocks there are separate clock oscillators dedicated to high speed serial I/O links (GTX/GTH, QSFP+, SATA) and external memories. All on-board clock lines use LVDS signalling to assure high level of signals integrity and immunity to distractions.

Hosting & Interfaces

Due to having of Xilinx Zynq-7000 interface FPGA on board it is possible to implement three kinds of hosting applications:

  • Embedded host with Zynq device and embedded Linux booted upon ARM cores running a testbench application that can drive AMBA AXI/AHB bus of the design or algorithm accelerator implemented in Kintex UltraScale.
  • External host PC with Zynq device running PCIe-to-AXI bridge connecting a host PC where testbench application is running with the design implemented in Kintex UltraScale.
  • Direct external host PC with PCIe interface accessing directly the Kintex UltraScale and being the part of the design or algorithm accelerator.

Aldec provides reusable hardware and software components in the Hes.Asic.Proto utilities bundle. For quick bring-up of embedded host scenario Aldec provides ready to use image of the Linux port for Zynq devices. In case of the external hosting Aldec’s Proto-AXI can be used, which consists of interface module IP with AMBA AXI interface and accompanying PCIe HES driver with high abstraction level C++ API for Linux and Windows PC. The board provides also a good selection of external interfaces like: USB 3.0 and USB 2.0, QSFP+, Gigabit Ethernet, SATA, FireFly for GTH. Another great additions are high precision ADC/DAC parts for DSP applications. The board has a compact form factor with standard PCI Express edge connector and PCIe 6-pin power supply connector so it can be attached directly to the main board of a PC Host computer.


Essential Features

FPGA & Capacity

  • Main FPGA: Kintex UltraScale XCKU115/XCKU085 (A1517 - 624I/O, 48 GTH)
    • XCKU115: 7.8 Million ASIC Gates (estimated for 60% of FPGA utilization)
  • Host FPGA: Zynq-7000 XC7Z100/XC7Z045/XC7Z035 (FFG900)

Flexible Clocking

  • 4 global clock modules with any-frequency clock synthesizers (Si5326)
    • 2 of global clocks connected to both UltraScale and Zynq FPGA
      • Low-skew, length aligned clock lines
  • 2 additional oscillators connected to Kintex Ultrascale main FPGA
  • 2 additional oscillators connected to Zynq-7000 host FPGA
  • 6 reference oscillators for DDR4 and RLD3 memories

Memory Resources

  • Memories connected to UltraScale FPGA
    • up to 32 GB of DDR4 (in two memory blocks)
    • 2.25 Gb of RLDRAM-3 in 4 modules
  • Memories connected to Zynq FPGA
    • 2 GB of DDR3 (1 GB for PS and 1 GB for PL)
    • Quad SPI Flash
    • Micro-SD slot

Interfaces & Hosting

  • Host interfaces connected to Zynq FPGA
    • PCIe x8, Gen 3
    • USB 2.0
    • UART
    • Gigabit Ethernet
  • Other peripherals connected to Zynq FPGA
    • ADC 8-bit, 500 MSPS (AD9484)
    • DAC 16-bit, 800 MSPS (DAC3283)
    • Misc: 4 LEDs, 8 Switches
  • Peripherals connected to UltraScale FPGA
    • ADC/DAC
    • 2x QSFP+
    • USB 3.0
    • 10x SATA (8x host, 2x device)
    • 2x FireFly connectors, each using 4 GTH high speed serial links
  • Board configuration and FPGA programming
    • Programming from Host
      • via PCIe (Aldec Hes.Asic.Proto application)
      • via JTAG (Xilinx utilities)
      • Programming from Micro-SD card or QSPI Flash
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