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Oct 05, 2017 OSVVM: ASIC level VHDL Verification, Simple enough for FPGAs (EU)

Time: 3:00 PM - 4:00 PM CEST

Abstract


Open Source VHDL Verification Methodology (OSVVM) provides an ASIC level VHDL verification methodology that is simple enough to use even on small FPGA projects. OSVVM offers the same capabilities as those based on other verification languages:

  • Transaction-Based Modeling
  • Constrained Random test generation
  • Functional Coverage with hooks for UCIS coverage database integration
  • Intelligent Coverage Random test generation
  • Utilities for testbench process synchronization
  • Transcript files
  • Error logging and reporting – Alerts and Affirmations
  • Message filtering – Logs
  • Scoreboards and FIFOs (data structures for verification)
  • Memory models

OSVVM is implemented as a library of free, open-source packages. It uses these packages to create features that rival language based implementations in both conciseness, simplicity, and capability.

Looking to improve your FPGA verification methodology? OSVVM provides a complete solution for VHDL ASIC or FPGA verification. There is no new language to learn. It is simple, powerful, and concise. Each piece is separate and can be used separately. Hence, you can learn and adopt pieces as you need them.



Agenda

This presentation will provide an overview of OSVVM's capabilities, including:

  • Transaction-Based Modeling (added in 2016.11*)
  • Constrained Random test generation
  • Functional Coverage
  • Intelligent Coverage Random test generation
  • Transcripts, Alerts, Logs, and Affirmations
  • Scoreboards and FIFOs (added in 2016.11*)
  • Memory models


While Transaction Based Modeling and Scoreboards were released to OSVVM in November 2016, they are mature capabilities that have been used for over 10+ years now in SynthWorks' VHDL Training classes.



Presenter Bio:

Jim Lewis, the founder of SynthWorks, has twenty-eight years of design, teaching, and problem solving experience. In addition to working as a Principal Trainer for SynthWorks, Mr. Lewis does ASIC and FPGA design, custom model development, and consulting. Mr Lewis is a founding member of the Open Source VHDL Verification Methodology (OSVVM) and the principal architect of its packages and methodology. Mr. Lewis, who holds a BSEE, BSCEE, and MSEE from Purdue University, serves as chair of the IEEE 1076 VHDL Analysis and Standardization Working Group (VASG).

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