Event Details

View All Recorded Events
Date Event Type 場所 Action
Apr 19, 2018 QEMU Co-emulation with FPGA (EU)

Time: 3:00 PM – 4:00 PM (CEST)



The FPGA or ASIC SoC require a robust pre-silicon hardware/software co-verification platform. Virtual platforms are used successfully as high-speed simulation vehicle but only for standard components like CPU, memory, timers and the like. The challenge emerges when custom IP-core is added to the design. Developing device drivers using HDL simulation is counterproductive and testing operating system and application stack is impossible. Hybrid co-emulation of standard machine virtualizer with FPGA bridges the gap in verification environment.


QEMU is a generic and open source machine emulator that supports various computer hardware architectures including Intel x86 and ARM® Cortex® families. It can be connected with the Aldec HES-DVM™ emulation platform to provide a hybrid co-emulation environment for SoC designs. We will demonstrate the latest QEMU Bridge designed to provide connection between CPU subsystem in QEMU and custom hardware IP-Core run in the HES FPGA board and mapped as PCI Express device in QEMU. We will also show how software stack GDB debugger can be used in step-lock mode with the Aldec Hardware Debugger to provide full and deterministic view of the entire SoC.



  • SoC Verification Challenges
  • Virtual Platform types and limitations
  • Emulation platform types and tradeoffs
  • Hybrid Co-emulation fix limitations & tradeoffs
  • Aldec QEMU Co-emulation Bridge
  • Live demo, Hardware-software co-verification on QEMU & HES-DVM Hybrid Platform
  • Conclusion
  • Q&A


Presenter Bio:

Krzysztof Szczur (aka Chris) is a Hardware Verification Products Manager at Aldec. Krzysztof joined Aldec in 2001 and was a key member of the team that developed HES-DVM™, Aldec's FPGA-based co-simulation, emulation and prototyping technology. In his engineering career he has also worked in the fields of HDL design verification, testbench automation and DO-254 compliance. Krzysztof has practical experience and a deep understanding of verification methodologies with hardware-in-the-loop and. Now, as the product manager, leverages this knowledge cooperating with key customers and Aldec's R&D team to bring innovations in Aldec’s hardware verification products. Krzysztof graduated as M.Eng. in Electronic Engineering (EE) at the AGH University of Science and Technology in Krakow, Poland.

ウェブセミナー Online More Info
Ask Us a Question
Ask Us a Question
Captcha ImageReload Captcha
Incorrect data entered.
Thank you! Your question has been submitted. Please allow 1-3 business days for someone to respond to your question.
Internal error occurred. Your question was not submitted. Please contact us using Feedback form.