Partners

Bitvis AS

Bitvis maintains UVVM – Universal VHDL Verification Methodology - a free, open source VHDL testbench library and methodology that significantly improves testbench structure and development – and thus also significantly reduces development time, improves overview, readability and maintainability, and is a major enabler for reuse. UVVM has a very low user threshold entry level that provides functionality for logging, alert handling, signal checking, signal expectance and BFM support. For systems with multiple interfaces, UVVM provides a VHDL Verification Component (VVC) Framework that is real game changer for VHDL verification, for the first time allowing a standardised and really well structured testbench architecture for providing stimuli on and checking multiple interfaces simultaneously – using structured verification components and very easily understandable commands to control them.

Bitvis also provides a three-day course on ‘Accelerating FPGA VHDL Verification’ and a two-day course on ‘Accelerating FPGA and Digital ASIC Design’.