Henderson, USA – November 26, 2019 – As design size and complexity grows, the design verification effort grows even more. It takes significant amount of time to thoroughly verify complex control logic of a design, which is the key and the most critical component of design functionality. One of the most common design patterns in the control logic design are finite state machines. They could be designed in different styles, state and output logic encodings, being either complex or simple for design, maintenance and verification. It is important to use the “Design-for-Verification” approach to develop Finite State Machines in a concise, robust and easy-to-verify way.
RTL code linting is the well-known approach ensuring design to be compliant with the collection of industry-best design guidelines for hardware development. Moreover, linting is able to automatically extract Finite State Machines structures from the design code and reveals FSM design bugs at the earliest stages of code development.
Standardizing FSM design patterns is an important part of RTL code standardization and it is widely used in many chip design houses. Lint tools formally verify the code to comply to company standards, avoiding design reviews and manual code check. Lint tools checks various FSM code features such as:
Lint tools automatically identify FSM code in RTL and extract FSM structure, presenting it in the FSM graph window. Designers visually approve the FSM design intent reviewing these FSM graphs. For the legacy code, extracted FSM graphs act as a design specification, allowing better understanding of the RTL code and facilitating its reuse. The following picture demonstrates the FSM graph extracted by Lint tools:
After FSM extraction, Lint tools apply various structural and functional checks to further verify FSM correctness and its compliance to company standards. For example, it is a good practice to avoid using Mealy and Mixed FSM types, preferring Moore FSM types only. Moore FSM outputs are registered and therefore they don’t propagate possible FSM input glitches to FSM outputs. Moore FSM are preferable from a timing perspective too, as FSM output timing paths include output decoding logic only. Also, it is a good practice to enforce a specific state encoding type to better fit a design into design requirements. For example, the one-hot encoding with Moore FSM type is preferable for the high-speed designs, while Gray encoding being preferable for the low-power applications, etc.
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