Munich, Germany – October 22, 2018 – Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for ASIC and FPGA designs, will present a tutorial entitled “Hardware and Software Co-verification in Hybrid HDL Simulation and Emulation Environment with QEMU” at the DVCon Europe Conference and Exhibition, to be held on October 24 and 25, 2018 in Munich, Germany.
Schedule: Wednesday, October 24, 4:00PM-5:30PM, Forum 5
Speakers: Radosław Nawrot, Aldec Inc. and Krzysztof Szczur, Aldec Inc.
In this tutorial Aldec will demonstrate the capabilities of its QEMU Bridge, which provides a connection between the virtual machine of a CPU subsystem (modelled in QEMU) and custom hardware designed in VHDL or Verilog which is simulated in Riviera-PRO™ and then emulated on an Aldec HES™ FPGA-based SoC/ASIC pre-silicon prototyping solution.
The company will also demonstrate how a software debugger (GDB) can be used in step-lock mode with Aldec’s hardware debugger to provide a holistic view of the entire SoC and thus facilitate the debugging, and by extension fixing, of the problems that typically arise if software and hardware engineers have different interpretations on the requirements spec’ and/or in handling last-minute changes as the development work progresses.
QEMU is a generic and open source machine emulator that supports various computer hardware architectures, including Intel x86 and ARM® Cortex® families. It can be connected with Aldec’s Riviera-PRO™ high performance HDL simulator and HES-DVM™, the FPGA-based emulation platform to provide a hybrid co-simulation and co-emulation environment for early hardware/software co-verification and embedded software development.
During the DVCon-EU Exhibition, Aldec will also demonstrate the latest additions to its capabilities within the overall verification spectrum: