By Bernard Murphy
You’re building an IP, subsystem or SoC and you want to use a prototype together with a software testbench to drive extensive validation testing. I’m not talking here about the software running on the IP/SoC processor(s); the testbench should wrap around the whole DUT. This is a very common requirement. The standard approach to addressing this need is to hook the prototype up to a host PC, run your testbench there and connect to the prototype through one of the standard interfaces.
But that's not necessarily ideal. Your real design probably has all kinds of communication interfaces to the rest of the system to which it will ultimately connect, yet you’re constrained to pushing all that testbench activity through a relatively narrow pipe between the prototype and the PC. Of course that can be done, but wouldn’t it be nice to have wider and more realistic channels to connect the testbench to the DUT? That’s what Aldec offers through their HES-US-440 prototyping board, hosting both a Xilinx UltraScale FPGA to prototype the DUT and a Xilinx Zynq FPGA to act as the testbench host...
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